First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering

Authors: Yu, X.-R., Chang, W.-H, Hong, T.-C., Sung, P.-J., Agarwal, A., Luo, G.-L., Wu, C.-T., Kao, K.-H., Su, C.-J., Chang, S.-W., Lu, W.-H., Fu, P.-Y., Lin, J.-H., Wu, P.-H., Cho, T.-C., Ma, W. C.-Yu., Lu, D.-D., Chao, T.-S., Maeda, T., Lee, Y.-J., Wu, W.-F., Yeh, W.-K., Wang, Y.-H.

Source: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2022 IEEE Symposium on. :399-400 Jun, 2022

Relation: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Investigation of AlGaN/GaN HEMT Breakdown analysis with Source field plate length for High power applications

Authors: Godfrey, D., Nirmal, D., Arivazhagan, L., Roy, B., Chen, Y.-L., Yu, T.-H., Yeh, W.-K., Godwinraj, D.

Source: 2020 5th International Conference on Devices, Circuits and Systems (ICDCS) Devices, Circuits and Systems (ICDCS), 2020 5th International Conference on. :244-246 Mar, 2020

Relation: 2020 5th International Conference on Devices, Circuits and Systems (ICDCS)

Sub-60 mV/dec Germanium Nanowire Field-Effect Transistors with 2-nm-thick Ferroelectric Hf0.5Zr0.5O2

Authors: Lin, Y.-W., Yu, T.-Y., Su, C.-J., Chen, Y.-N., Chang, H.-H., Luo, G.-L., Wu, C.-T., Wu, W.-F., Lin, K.-L., Hou, F.-J., Wu, Y.-C., Yeh, W.-K.

Source: 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) VLSI Technology, Systems and Applications (VLSI-TSA), 2021 International Symposium on. :1-2 Apr, 2021

Relation: 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

CMOS-MEMS multi-sensor single chip with high heat dissipation and low-temperature hermetic sealing

Authors: Chang, C. Y., Tseng, S. H., Chiang, M. H., Hsin, C. T., Ke, L. Y., Wang, Y. J., Yeh, C. Y., Tsai, H. H., Juang, Y. Z., Yeh, W. K.

Source: 2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :23.5.1-23.5.4 Dec, 2021

Relation: 2021 IEEE International Electron Devices Meeting (IEDM)

First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications

Authors: Chang, S.-W., Lu, T.-H., Yang, C.-Y., Yeh, C.-J., Huang, M.-K., Meng, C.-F., Chen, P.-J., Chang, T.-H., Chang, Y.-S., Jhu, J.-W., Hong, T.-Z., Ke, C.-C., Yu, X.-R., Lu, W.-H., Baig, M. A., Cho, T.-C., Sung, P.-J., Su, C.-J., Hsueh, F.-K., Chen, B.-Y., Hu, H.-H., Wu, C.-T., Lin, K.-L., Ma, W. C.-Y., Lu, D.-D., Kao, K.-H., Lee, Y.-J., Lin, C.-L., Huang, K.-P., Chen, K.-M., Li, Y., Samukawa, S., Chao, T.-S., Huang, G.-W., Wu, W.-F., Lee, W.-H., Li, J.-Y., Shieh, J.-M., Tarng, J.-H., Wang, Y.-H., Yeh, W.-K.

Source: 2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :34.4.1-34.4.4 Dec, 2021

Relation: 2021 IEEE International Electron Devices Meeting (IEDM)

Ge FinFET CMOS Inverters with Improved Channel Surface Roughness by Using In-situ ALD Digital O3 Treatment

Authors: Yeh, M.-S., Luo, G.-L., Hou, F.-J., Sung, P.-J., Wang, C.-J., Su, C.-J., Wu, C.-T., Huang, Y.-C., Hong, T.-C., Chao, T.-S., Chen, B.-Y., Chen, K.-M., Izawa, M., Miura, M., Morimoto, M., Ishimura, H., Lee, Y.-J., Wu, W.-F., Yeh, W.-K.

Source: 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) Electron Devices Technology and Manufacturing Conference (EDTM), 2018 IEEE 2nd. :205-207 Mar, 2018

Relation: 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)

3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers

Authors: Su, C. J., Huang, M. K., Lee, K. S., Hu, V. P. H., Huang, Y. F., Zheng, B. C., Yao, C. H., Lin, N. C., Kao, K. H., Hong, T. C., Sung, P. J., Wu, C. T., Yu, T. Y., Lin, K. L., Tseng, Y. C., Lin, C. L., Lee, Y. J., Chao, T. S., Li, J. Y., Wu, W. F., Shieh, J. M., Wang, Y. H., Yeh, W. K.

Source: 2020 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2020 IEEE International. :12.2.1-12.2.4 Dec, 2020

Relation: 2020 IEEE International Electron Devices Meeting (IEDM)

First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)

Authors: Hong, T.-Z., Chang, W.-H., Agarwal, A., Huang, Y.-T., Yang, C.-Y., Chu, T.-Y., Chao, H.-Y., Chuang, Y., Chung, S.-T., Lin, J.-H., Luo, S.-M., Tsai, C.-J., Li, M.-J., Yu, X.-R., Lin, N.-C., Cho, T.-C., Sung, P.-J., Su, C.-J., Luo, G.-L., Hsueh, F.-K., Lin, K.-L., Ishii, H., Irisawa, T., Maeda, T., Wu, C.-T., Ma, W. C.-Y., Lu, D.-D., Kao, K.-H., Lee, Y.-J., Chen, H. J.-H., Lin, C.-L., Chuang, R. W., Huang, K.-P., Samukawa, S., Li, Y.-M., Tarng, J.-H., Chao, T.-S., Miura, M., Huang, G.-W., Wu, W.-F., Li, J.-Y., Shieh, J.-M., Wang, Y.-H., Yeh, W.-K.

Source: 2020 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2020 IEEE International. :15.5.1-15.5.4 Dec, 2020

Relation: 2020 IEEE International Electron Devices Meeting (IEDM)

A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs

Authors: Tang, Y.-T, Fan, C.-L., Kao, Y.-C., Modolo, N., Su, C.-J., Wu, T.-L., Kao, K.-H., Wu, P.-J., Hsaio, S.-W., Useinov, A., Su, Pin, Wu, W.-F., Huang, G.-W., Shieh, J.-M., Yeh, W.-K., Wang, Y.-H.

Source: 2019 Symposium on VLSI Technology VLSI Technology, 2019 Symposium on. :T222-T223 Jun, 2019

Relation: 2019 Symposium on VLSI Technology

Fabrication of $\Omega$ -gated Negative Capacitance FinFETs and SRAM

Authors: Sung, P.-J., Su, C.-J., Lu, D. D., Luo, S.-X., Kao, K.-H., Ciou, J.-Y., Jao, C.-Y., Hsu, H.-S., Wang, C.-J., Hong, T.-C., Liao, T.-H., Fang, C.-C., Wang, Y.-S., Huang, H.-F., Li, J.-H., Huang, Y.-C., Hsueh, F.-K., Wu, C.-T., Ma, W. C.-Y., Huang, K.-P., Lee, Y.-J., Chao, T.-S., Li, J.-Y., Wu, W.-F., Yeh, W.-K., Wang, Y.-H.

Source: 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) VLSI Technology, Systems and Application (VLSI-TSA), 2019 International Symposium on. :1-2 Apr, 2019

Relation: 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

Study of sub-5 nm RRAM, tunneling selector and selector less device

Authors: Li, Kai-Shin, Lee, Ming-Taou, Chen, Min-Cheng, Hsu, Cho-Lun, Lu, J. M., Lin, C. H., Chen, C. C., Wu, B. W., Hou, Y. F., Lin, C. Yi., Chen, Y. J., Lai, T. Y., Li, M. Y., Yang, I., Wu, C. S., Yang, Fu-Liang, Yeh, W. K.

Source: 2015 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2015 IEEE International Symposium on. :385-388 May, 2015

Relation: 2015 IEEE International Symposium on Circuits and Systems (ISCAS)

A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node

Authors: Tang, Y.-T, Su, C.-J., Wang, Y.-S., Kao, K.-H., Wu, T.-L., Sung, P.-J., Hou, F.-J., Wang, C.-J., Yeh, M.-S., Lee, Y.-J., Wu, W.-F., Huang, G.-W., Shieh, J.-M., Yeh, W.-K., Wang, Y.-H.

Source: 2018 IEEE Symposium on VLSI Technology VLSI Technology, 2018 IEEE Symposium on. :45-46 Jun, 2018

Relation: 2018 IEEE Symposium on VLSI Technology

First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

Authors: Chang, S.-W., Sung, P.-J., Chu, T-Y., Lu, D. D., Wang, C.-J., Lin, N.-C., Su, C.-J., Lo, S.-H., Huang, H.-F., Li, J.-H., Huang, M.-K., Huang, Y.-C., Huang, S.-T., Wang, H.-C., Huang, Y.-J., Wang, J.-Y., Yu, L. - W, Huang, Y.-F., Hsueh, F. - K., Wu, C.-T., Ma, W. C.-Y., Kao, K.-H., Lee, Y. - J., Lin, C.-L., Chuang, R. W., Huang, K.-P., Samukawa, S., Li, Y., Lee, W. - H., Chao, T.-S., Huang, G. - W., Wu, W.-F., Li, J. - Y., Shieh, J.-M., Yeh, W. - K., Wang, Y.-H.

Source: 2019 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2019 IEEE International. :11.7.1-11.7.4 Dec, 2019

Relation: 2019 IEEE International Electron Devices Meeting (IEDM)

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION

Authors: Su, C.-J., Tang, Y.-T, Tsou, Y.-C., Sung, P.-J., Hou, F.-J., Wang, C.-J., Chung, S.-T., Hsieh, C.-Y., Yeh, Y.-S., Hsueh, F.-K., Kao, K.-H., Chuang, S.-S., Wu, C.-T., You, T.-Y., Jian, Y.-L., Chou, T.-H., Shen, Y.-L., Chen, B.-Y., Luo, G.-L., Hong, T.-C., Huang, K.-P., Chen, M.-C., Lee, Y.-J., Chao, T.-S., Tseng, T.-Y., Wu, W.-F., Huang, G.-W., Shieh, J.-M., Yeh, W.-K., Wang, Y.-H.

Source: 2017 Symposium on VLSI Technology VLSI Technology, 2017 Symposium on. :T152-T153 Jun, 2017

Relation: 2017 Symposium on VLSI Technology

Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

Authors: Sung, P.-J., Chang, C.-Y., Chen, L.-Y., Kao, K.-H., Su, C.-J., Liao, T.-H., Fang, C.-C., Wang, C.-J., Hong, T.-C., Jao, C.-Y., Hsu, H.-S., Luo, S.-X., Wang, Y.-S., Huang, H.-F., Li, J.-H., Huang, Y.-C., Hsueh, F.-K., Wu, C.-T., Huang, Y.-M., Hou, F.-J., Luo, G.-L., Shen, Y.-L., Ma, W. C.-Y., Huang, K.-P., Lin, K.-L., Samukawa, S., Li, Y., Huang, G.-W, Lee, Y.-J., Li, J.-Y., Wu, W.-F., Shieh, J.-M., Chao, T.-S., Yeh, W.-K., Wang, Y.-H.

Source: 2018 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2018 IEEE International. :21.4.1-21.4.4 Dec, 2018

Relation: 2018 IEEE International Electron Devices Meeting (IEDM)

The impact of mobility modulation technology on device performance and reliability for sub-90nm SOI MOSFETs

Authors: Yeh, W.-K., Lai, C.-M., Lin, C.-T., Fang, Y.-K., Hu, H.-H., Chen, K.-M., Huang, G.-W.

Source: 2005 IEEE Conference on Electron Devices and Solid-State Circuits Electron Devices and Solid-State Circuits, 2005 IEEE Conference on. :91-94 2005

Relation: 2005 IEEE Conference on Electron Devices and Solid-State Circuits

High performance silicon N-channel gate-all-around junctionless field effect transistors by strain technology

Authors: Sung, P.-J., Cho, T.-C., Chen, P.-C., Hou, F.-J., Lai, C.-H, Lee, Y.-J., Li, Y., Samukawa, S., Chao, T.-S., Wu, W.-F., Yeh, W.-K.

Source: 2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO) Nanotechnology (IEEE-NANO), 2016 IEEE 16th International Conference on. :174-175 Aug, 2016

Relation: 2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO)

Effects of Fin Width on Device Performance and Reliability of Double-Gate n-Type FinFETs

Authors: Lin, C.-L., Hsiao, P.-H., Yeh, W.-K., Liu, H.-W., Yang, S.-R., Chen, Y.-T., Chen, K.-M., Liao, W.-S.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 60(11):3639-3644 Nov, 2013

Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

Authors: Su, C.-J., Hong, T.-C., Tsou, Y.-C., Hou, F.-J., Sung, P.-J., Yeh, M.-S., Wan, C.-C., Kao, K.-H., Tang, Y.-T., Chiu, C.-H., Wang, C.-J., Chung, S.-T., You, T.-Y., Huang, Y.-C., Wu, C.-T., Lin, K.-L., Luo, G.-L., Huang, K.-P., Lee, Y.-J., Chao, T.-S., Wu, W.-F., Huang, G.-W., Shieh, J.-M., Yeh, W.-K., Wang, Y.-H.

Source: 2017 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2017 IEEE International. :15.4.1-15.4.4 Dec, 2017

Relation: 2017 IEEE International Electron Devices Meeting (IEDM)

Experimental Verification of RF Stress Effect on Cascode Class-E PA Performance and Reliability

Authors: Yuan, J.-S., Yen, H.-D., Chen, S., Wang, R.-L., Huang, G.-W., Juang, Y.-Z., Tu, C.-H., Yeh, W.-K., Ma, J.

Source: IEEE Transactions on Device and Materials Reliability IEEE Trans. Device Mater. Relib. Device and Materials Reliability, IEEE Transactions on. 12(2):369-375 Jun, 2012