Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning

Authors: Kim, Y., Seo, S., Consiglio, S., Jamison, P., Higuchi, H., Rasch, M., Wu, E.Y., Kong, D., Saraf, I., Catano, C., Muralidhar, R., Nguyen, S., DeVries, S., Van der Straten, O., Sankarapandian, M., Pujari, R.N., Gasasira, A., Mcdermott, S.M., Miyazoe, H., Koty, D., Yang, Q., Yan, H., Clark, R., Tapily, K., Engelmann, S., Robison, R.R., Wajda, C., Mosden, A., Tsunomura, T., Soave, R., Saulnier, N., Haensch, W., Leusink, G., Biolsi, P., Narayanan, V., Ando, T.

Source: IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 42(5):759-762 May, 2021

Exploring the Limits of Cobalt Liner Thickness in Advanced Copper Interconnects

Authors: Lanzillo, N.A., Yang, C., Motoyama, K., Huang, H., Cheng, K., Maniscalco, J., Van Der Straten, O., Penny, C., Standaert, T., Choi, K.

Source: IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 40(11):1804-1807 Nov, 2019

First Experimental Demonstration of MRAM Data Scrubbing: 80 Mb MRAM with 40 nm junctions for Last Level Cache Applications

Authors: Wu, H., Katragadda, V., Evarts, E., Edwards, E., Southwick, R., Dutta, A., Lauer, G., Mehta, V., Johnson, R., van der Straten, O., Reznicek, A., Wordeman, M., Rizzolo, M., Patlolla, R., Metzler, D., Yang, C., Edelstein, D., Canaperi, D., Teehan, S., Slaughter, J.M., Worledge, D.C.

Source: 2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :2.3.1-2.3.4 Dec, 2021

Relation: 2021 IEEE International Electron Devices Meeting (IEDM)

Ru Liner Scaling with ALD TaN Barrier Process for Low Resistance 7 nm Cu Interconnects and Beyond

Authors: Motoyama, K., van der Straten, O., Maniscalco, J., Huang, H., Kim, YB., Choi, JK., Lee, JH., Hu, C.-K., McLaughlin, P., Standaert, T., Quon, R., Bonilla, G.

Source: 2018 IEEE International Interconnect Technology Conference (IITC) Interconnect Technology Conference (IITC), 2018 IEEE International. :40-42 Jun, 2018

Relation: 2018 IEEE International Interconnect Technology Conference (IITC)

A 14 nm Embedded STT-MRAM CMOS Technology

Authors: Edelstein, D., Rizzolo, M., Sil, D., Dutta, A., DeBrosse, J., Wordeman, M., Arceo, A., Chu, I. C., Demarest, J., Edwards, E. R. J., Evarts, E. R., Fullam, J., Gasasira, A., Hu, G., Iwatake, M., Johnson, R., Katragadda, V., Levin, T., Li, J., Liu, Y., Long, C., Maffitt, T., McDermott, S., Mehta, S., Mehta, V., Metzler, D., Morillo, J., Nakamura, Y., Nguyen, S., Nieves, P., Pai, V., Patlolla, R., Pujari, R., Southwick, R., Standaert, T., van der Straten, O., Wu, H., Yang, C.-C., Houssameddine, D., Slaughter, J. M., Worledge, D. C.

Source: 2020 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2020 IEEE International. :11.5.1-11.5.4 Dec, 2020

Relation: 2020 IEEE International Electron Devices Meeting (IEDM)

BEOL process integration for the 7 nm technology node

Authors: Standaert, T., Beique, G., Chen, H.-C., Chen, S.-T., Hamieh, B., Lee, J., McLaughlin, P., McMahon, J., Mignot, Y., Mont, F., Motoyama, K., Nguyen, S., Patlolla, R., Peethala, B., Priyadarshini, D., Rizzolo, M., Saulnier, N., Shobha, H., Siddiqui, S., Spooner, T., Tang, H., van der Straten, O., Verduijn, E., Xu, Y., Zhang, X., Arnold, J., Canaperi, D., Colburn, M., Edelstein, D., Paruchuri, V., Bonilla, G.

Source: 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC) Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2016 IEEE International. :2-4 May, 2016

Relation: 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC)

Novel Cu reflow seed process for Cu/low-k 64nm pitch dual damascene interconnects and beyond

Authors: Motoyama, K., van der Straten, O., Tomizawa, H., Maniscalco, J., Chen, S.T.

Source: 2012 IEEE International Interconnect Technology Conference Interconnect Technology Conference (IITC), 2012 IEEE International. :1-3 Jun, 2012

Relation: 2012 IEEE International Interconnect Technology Conference - IITC

64 nm pitch Cu dual-damascene interconnects using pitch split double exposure patterning scheme

Authors: Shyng-Tsong Chen, Tomizawa, H., Tsumura, K., Tagami, M., Shobha, H., Sankarapandian, M., Van der Straten, O., Kelly, J., Canaperi, D., Levin, T., Cohen, S., Yin, Y., Horak, D., Ishikawa, M., Mignot, Y., Koay, C-S., Burns, S., Halle, S., Kato, H., Landie, G., Xu, Y., Scaduto, A., Mclellan, E., Arnold, J.C., Colburn, M., Usui, T., Spooner, T.

Source: 2011 IEEE International Interconnect Technology Conference Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International. :1-3 May, 2011

Relation: Joint 2011 IEEE International Interconnect Technology Conference (IITC) & 2011 Materials for Advanced Metallization (MAM)

Robust self-aligned via process for 64nm pitch Dual-Damascene interconnects using pitch split double exposure patterning scheme

Authors: Tomizawa, H., Chen, S.T., Horak, D., Kato, H., Yin, Y., Ishikawa, M., Kelly, J., Koay, C.S., Landie, G., Burns, S., Tsumura, K., Tagami, M., Shobha, H., Sankarapandian, M., van der Straten, O., Maniscalco, J., Vo, T., Arnold, J., Colburn, M., Usui, T., Spooner, T.

Source: 2011 IEEE International Interconnect Technology Conference Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International. :1-3 May, 2011

Relation: Joint 2011 IEEE International Interconnect Technology Conference (IITC) & 2011 Materials for Advanced Metallization (MAM)

Thermal and electrical barrier performance testing of ultrathin atomic layer deposition tantalum-based materials for nanoscale copper metallization

Authors: van der Straten, O., Zhu, Y., Eisenbraun, E., Kaloyeros, A.

Source: Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519) Interconnect technology conference Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International. :188-190 2002

Relation: Proceedings of the IEEE 2002 International Interconnect Technology Conference

Atomic layer deposition (ALD) of tantalum-based materials for zero thickness copper barrier applications

Authors: Eisenbraun, E., van der Straten, O., Yu Zhu, Dovidenko, K., Kaloyeros, A.

Source: Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461) Interconnect technology conference Interconnect Technology Conference, 2001. Proceedings of the IEEE 2001 International. :207-209 2001

Relation: Proceedings of the IEEE 2001 International Interconnect Technology Conference

Evaluation of Cu surface diffusion on different metal liner materials for Cu reflow applications.

Authors: van der Straten, O., Wangoh, L. W.

Source: Journal of Materials Research; Oct2024, Vol. 39 Issue 20, p2811-2819, 9p

Application of Cu Reflow Process on Ru Liner for Advanced Nanoscale Interconnects

Authors: Motoyama, K., van der Straten, O.

Source: ECS Journal of Solid State Science and Technology; September 2024, Vol. 13 Issue: 9 p094001-094001, 1p

Robust TaNx diffusion barrier for Cu-interconnect technology with subnanometer thickness by metal-organic plasma-enhanced atomic layer deposition.

Authors: Kim, H., Detavenier, C., van der Straten, O., Rossnagel, S. M., Kellock, A. J., Park, D.-G.

Source: Journal of Applied Physics; 7/1/2005, Vol. 98 Issue 1, p014308, 8p, 4 Black and White Photographs, 5 Graphs

Subject Terms: HYDROGEN, NITROGEN plasmas, PLASMA gases, IONIZED gases, MICROSTRUCTURE, CONSTITUTION of matter

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