10nm FINFET technology for low power and high performance applications

Authors: Guo, D., Shang, H., Seo, K., Haran, B., Standaert, T., Gupta, D., Alptekin, E., Bae, D., Bae, G., Chanemougame, D., Cheng, K., Cho, J., Hamieh, B., Hong, J., Hook, T., Jung, J., Kambhampati, R., Kim, B., Kim, H., Kim, K., Kim, T., Liu, D., Mallela, H., Montanini, P., Mottura, M., Nam, S., Ok, I., Park, Y., Paul, A., Prindle, C., Ramachandran, R., Sardesai, V., Scholze, A., Seo, S., Southwick, R., Strane, J., Sun, X., Tsutsui, G., Tripathi, N., Vega, R., Weybright, M., Xie, R., Yeh, C., Bu, H., Burns, S., Canaperi, D., Celik, M., Colburn, M., Jagannathan, H., Kanakasabaphthy, S., Kleemeier, W., Liebmann, L., Mcherron, D., Oldiges, P., Paruchuri, V., Spooner, T., Stathis, J., Divakaruni, R., Gow, T., Iacoponi, J., Jenq, J., Sampson, R, Yang, W., Khare, M.

Source: 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on. :1-4 Oct, 2014

Relation: 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT)

Therapeutic Inertia in the Management of Psoriasis: A Quantitative Survey Among Indian Dermatologists and Patients

Authors: Rajagopalan M, Dogra S, Godse K, Kar BR, Kotla SK, Neema S, Saraswat A, Shah SD, Madnani N, Sardesai V, Sekhri R, Varma S, Arora S, Kawatra P

Source: Psoriasis: Targets and Therapy, Vol Volume 12, Pp 221-230 (2022)

Subject Terms: therapeutic inertia, psoriasis, adherence, treatment expectations, treatment goals, diagnosis, Dermatology, RL1-803

File Description: electronic resource

Relation: https://www.dovepress.com/therapeutic-inertia-in-the-management-of-psoriasis-a-quantitative-surv-peer-reviewed-fulltext-article-PTT; https://doaj.org/toc/2230-326X

Access URL: https://doaj.org/article/57b6a04ee828411fa6fa03eaacf0d49f

Ti and NiPt/Ti liner silicide contacts for advanced technologies

Authors: Adusumilli, P., Alptekin, E., Raymond, M., Breil, N., Chafik, F., Lavoie, C., Ferrer, D., Jain, S., Kamineni, V., Ozcan, A., Allen, S., An, J. J., Basker, V., Bolam, R., Bu, H., Cai, J., Demarest, J., Doris, B., Engbrecht, E., Fan, S., Fronheiser, J., Gluschenkov, O., Guo, D., Haran, B., Hilscher, D., Jagannathan, H., Kang, D., Ke, Y., Kim, J., Koswatta, S., Kumar, A., Labonte, A., Lallement, R., Lee, W., Lee, Y., Li, J., Lin, C-H, Liu, B., Liu, Z., Loubet, N., Makela, N., Mochizuki, S., Morgenfeld, B., Narasimha, S., Nesheiwat, T., Niimi, H., Niu, C., Oh, M., Park, C., Ramachandran, R., Rice, J., Sardesai, V., Shearer, J., Sheraw, C., Tran, C., Tsutsui, G., Utomo, H., Wong, K., Xie, R., Yamashita, T., Yan, Y., Yeh, C., Yu, M., Zamdmer, N., Zhan, N., Zhang, B., Paruchuri, V., Goldberg, C., Kleemeier, W., Stiffler, S., Divakaruni, R., Henson, W.

Source: 2016 IEEE Symposium on VLSI Technology VLSI Technology, 2016 IEEE Symposium on. :1-2 Jun, 2016

Relation: 2016 IEEE Symposium on VLSI Technology

A 7nm CMOS technology platform for mobile and high performance compute application

Authors: Narasimha, S., Jagannathan, B., Ogino, A., Jaeger, D., Greene, B., Sheraw, C., Zhao, K., Haran, B., Kwon, U., Mahalingam, A. K. M., Kannan, B., Morganfeld, B., Dechene, J., Radens, C., Tessier, A., Hassan, A., Narisetty, H., Ahsan, I., Aminpur, M., An, C., Aquilino, M., Arya, A., Augur, R., Baliga, N., Bhelkar, R., Biery, G., Blauberg, A., Borjemscaia, N., Bryant, A., Cao, L., Chauhan, V., Chen, M., Cheng, L., Choo, J., Christiansen, C., Chu, T., Cohen, B., Coleman, R., Conklin, D., Crown, S., da Silva, A., Dechene, D., Derderian, G., Deshpande, S., Dilliway, G., Donegan, K., Eller, M., Fan, Y., Fang, Q., Gassaria, A., Gauthier, R., Ghosh, S., Gifford, G., Gordon, T., Gribelyuk, M., Han, G., Han, J.H., Han, K., Hasan, M., Higman, J., Holt, J., Hu, L., Huang, L., Huang, C., Hung, T., Jin, Y., Johnson, J., Johnson, S., Joshi, V., Joshi, M., Justison, P., Kalaga, S., Kim, T., Kim, W., Krishnan, R., Krishnan, B., Anil, K., Kumar, M., Lee, J., Lee, R., Lemon, J., Liew, S.L., Lindo, P., Lingalugari, M., Lipinski, M., Liu, P., Liu, J., Lucarini, S., Ma, W., Maciejewski, E., Madisetti, S., Malinowski, A., Mehta, J., Meng, C., Mitra, S., Montgomery, C., Nayfeh, H., Nigam, T., Northrop, G., Onishi, K., Ordonio, C., Ozbek, M., Pal, R., Parihar, S., Patterson, O., Ramanathan, E., Ramirez, I., Ranjan, R., Sarad, J., Sardesai, V., Saudari, S., Schiller, C., Senapati, B., Serrau, C., Shah, N., Shen, T., Sheng, H., Shepard, J., Shi, Y., Silvestre, M.C., Singh, D., Song, Z., Sporre, J., Srinivasan, P., Sun, Z., Sutton, A., Sweeney, R., Tabakman, K., Tan, M., Wang, X., Woodard, E., Xu, G., Xu, D., Xuan, T., Yan, Y., Yang, J., Yeap, K.B., Yu, M., Zainuddin, A., Zeng, J., Zhang, K., Zhao, M., Zhong, Y., Carter, R., Lin, C.-H., Grunow, S., Child, C., Lagus, M., Fox, R., Kaste, E., Gomba, G., Samavedam, S., Agnello, P., Sohn, D. K.

Source: 2017 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2017 IEEE International. :29.5.1-29.5.4 Dec, 2017

Relation: 2017 IEEE International Electron Devices Meeting (IEDM)

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Authors: Seo, K. -I., Haran, B., Gupta, D., Guo, D., Standaert, T., Xie, R., Shang, H., Alptekin, E., Bae, D. -I., Bae, G., Boye, C., Cai, H., Chanemougame, D., Chao, R., Cheng, K., Cho, J., Choi, K., Hamieh, B., Hong, J. G., Hook, T., Jang, L., Jung, J., Jung, R., Lee, D., Lherron, B., Kambhampati, R., Kim, B., Kim, H., Kim, K., Kim, T. S., Ko, S.-B., Lie, F. L., Liu, D., Mallela, H., Mclellan, E., Mehta, S., Montanini, P., Mottura, M., Nam, J., Nam, S., Nelson, F., Ok, I., Park, C., Park, Y., Paul, A., Prindle, C., Ramachandran, R., Sankarapandian, M., Sardesai, V., Scholze, A., Seo, S. -C, Shearer, J., Southwick, R., Sreenivasan, R., Stieg, S., Strane, J., Sun, X., Sung, M. G., Surisetty, C., Tsutsui, G., Tripathi, N., Vega, R., Waskiewicz, C., Weybright, M., Yeh, C.-C., Bu, H., Burns, S., Canaperi, D., Celik, M., Colburn, M., Jagannathan, H., Kanakasabaphthy, S., Kleemeier, W., Liebmann, L., Mcherron, D., Oldiges, P., Paruchuri, V., Spooner, T., Stathis, J., Divakaruni, R., Gow, T., Iacoponi, J., Jenq, J., Sampson, R., Khare, M.

Source: 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on. :1-2 Jun, 2014

Relation: 2014 IEEE Symposium on VLSI Technology

A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate

Authors: Yuan, J., Chan, V., Eller, M., Rovedo, N., Lee, H. K., Gao, Y., Sardesai, V., Kanike, N., Vidya, V., Kwon, O., Kwon, O. S., Yan, J., Fang, S., Wille, W., Wang, H., Chow, Y. T., Booth, R., Kebede, T., Clark, W., Mo, H., Ryou, C., Liang, J., Yang, J. H., Lai, C.W., Naragad, S.S., Gluschenkov, O., Visokay, M. R., Radens, C., Deshpande, S., Shang, H., Li, Y., Cave, N., Sudijono, J., Ku, J., Divakaruni, R.

Source: 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on. :1130-1133 Oct, 2008

Relation: 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT)

Blanket SMT With In Situ N2 Plasma Treatment on the $\langle \hbox{100} \rangle$ Wafer for the Low-Cost Low-Power Technology Application

Authors: Yuan, J., Chan, V., Rovedo, N., Sardesai, V., Kanike, N., Varadarajan, V., Yu, M., Yang, J. H., Jeong, Y. K., Kwon, O. S., Belyansky, M. P., Eller, M., Lee, Y. M., Cave, N., Shang, H., Li, Y., Divakaruni, R.

Source: IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 30(9):916-918 Sep, 2009

High performance bulk planar 20nm CMOS technology for low power mobile applications

Authors: Shang, Huiling, Jain, S., Josse, E., Alptekin, E., Nam, M.H., Kim, S.W., Cho, K.H., Kim, I., Liu, Y., Yang, X., Wu, X., Ciavatti, J., Kim, N.S., Vega, R., Kang, L., Meer, H.V., Samavedam, S., Celik, M., Soss, S., Utomo, H., Ramachandran, R., Lai, W., Sardesai, V., Tran, C., Kim, J.Y., Park, Y.H., Tan, W.L., Shimizu, T., Joy, R., Strane, J., Tabakman, K., Lalanne, F., Montanini, P., Babich, K., Kim, J. B., Economikos, L., Cote, W., Reddy, C., Belyansky, M., Arndt, R., Kwon, U., Wong, K., Koli, D., Levedakis, D., Lee, J.W., Muncy, J., Krishnan, S., Schepis, D., Chen, X., Kim, B.D., Tian, C., Linder, B.P., Cartier, E., Narayanan, V., Northrop, G., Menut, O., Meiring, J., Thomas, A., Aminpur, M., Park, S.H., Lee, K.Y., Kim, B.Y., Rhee, S.H., Hamieh, B., Srivastava, R., Koshy, R., Goldberg, C., Pallachalil, M., Chae, M., Ogino, A., Watanabe, T., Oh, M., Mallela, H., Codi, D., Malinge, P., Weybright, M., Mann, R., Mittal, A., Eller, M., Lian, S., Li, Y., Divakaruni, R., Bukofsky, S., Kim, J.D., Sudijono, J., Neumueller, W., Matsuoka, F., Sampson, R.

Source: 2012 Symposium on VLSI Technology (VLSIT) VLSI Technology (VLSIT), 2012 Symposium on. :129-130 Jun, 2012

Relation: 2012 IEEE Symposium on VLSI Technology

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

Authors: Lin, C-H., Greene, B., Narasimha, S., Cai, J., Bryant, A., Radens, C., Narayanan, V., Linder, B., Ho, H., Aiyar, A., Alptekin, E., An, J-J., Aquilino, M., Bao, R., Basker, V., Breil, N., Brodsky, M., Chang, W., Clevenger, L., Chidambarrao, D., Christiansen, C., Conklin, D., DeWan, C., Dong, H., Economikos, L., Engel, B., Fang, S., Ferrer, D., Friedman, A., Gabor, A., Guarin, F., Guan, X., Hasanuzzaman, M., Hong, J., Hoyos, D., Jagannathan, B., Jain, S., Jeng, S-J., Johnson, J., Kannan, B., Ke, Y., Khan, B., Kim, B., Koswatta, S., Kumar, A., Kwon, T., Kwon, U., Lanzerotti, L., Lee, H-K, Lee, W-H., Levesque, A., Li, W., Li, Z., Liu, W., Mahajan, S., McStay, K., Nayfeh, H., Nicoll, W., Northrop, G., Ogino, A., Pei, C., Polvino, S., Ramachandran, R., Ren, Z., Robison, R., Saraf, I., Sardesai, V., Saudari, S., Schepis, D., Sheraw, C., Siddiqui, S., Song, L., Stein, K., Tran, C., Utomo, H., Vega, R., Wang, G., Wang, H., Wang, W., Wang, X., Wehelle-Gamage, D., Woodard, E., Xu, Y., Yang, Y., Zhan, N., Zhao, K., Zhu, C., Boyd, K., Engbrecht, E., Henson, K., Kaste, E., Krishnan, S., Maciejewski, E., Shang, H., Zamdmer, N., Divakaruni, R., Rice, J., Stiffler, S., Agnello, P.

Source: 2014 IEEE International Electron Devices Meeting Electron Devices Meeting (IEDM), 2014 IEEE International. :3.8.1-3.8.3 Dec, 2014

Relation: 2014 IEEE International Electron Devices Meeting (IEDM)

A 45nm Low Cost Low Power Platform by Using Integrated Dual-Stress-Liner Technology

Authors: Yuan, J., Tan, S., Lee, Y., Kim, J., Lindsay, R., Sardesai, V., Hook, T., Amos, R., Luo, Z., Lee, W., Fang, S., Dyer, T., Rovedo, N., Stierstorfer, R., Yang, Z., Li, J., Barton, K., Ng, H., Sudijono, J., Ku, J., Hierlemann, M., Schiml, T.

Source: 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on. :100-101 2006

Relation: 2006 Symposium on VLSI Technology

Assessment of fully-depleted planar CMOS for low power complex circuit operation

Authors: Ren, Z., Mehta, S., Cai, J., Wu, S., Zhu, Y., Kanarsky, T., Kanakasabapathy, S., Edge, L.F., Zhang, R., Lindo, P., Koshy, J., Tabakman, K., Kulkarni, P., Sardesai, V., Cheng, K., Khakifirooz, A., Doris, B., Bu, H., Park, D.-G.

Source: 2011 International Electron Devices Meeting Electron Devices Meeting (IEDM), 2011 IEEE International. :15.5.1-15.5.4 Dec, 2011

Relation: 2011 IEEE International Electron Devices Meeting (IEDM)

An evaluation of Cu wiring in a production 64 Mb DRAM

Authors: Cote, W., Costrini, G., Edelstein, D., Osborn, C., Poindexter, D., Sardesai, V., Bronner, G.

Source: 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) VLSI technology VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on. :24-25 1998

Relation: 1998 Symposium on VLSI Technology Digest of Technical Papers

IPTC 16646 Asset Integrity Challenges in Oil & Gas Process Facilities
International petroleum technology

Authors: Al-Sulaiman, S., Sardesai, V., Murthy, H.S., Reddy, N.H., John, R.P.

Source: INTERNATIONAL PETROLEUM TECHNOLOGY CONFERENCE. 2:1673-1681

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN084852749&indx=1&recIds=ETOCCN084852749

IPTC 14434 Risk Based Inspection (RBI) of Aboveground Storage Tanks to Improve Asset Integrity
International petroleum technology; (IPTC 2012)

Authors: Al-Mithin, A.W., Sardesai, V., Al-Harbi, B., Murthy, H.S., Hannan, A.S.A.

Source: INTERNATIONAL PETROLEUM TECHNOLOGY CONFERENCE. 1:750-755

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN081719300&indx=1&recIds=ETOCCN081719300

PVP2010-25115 Integrity Management of Aged Equipment in Sour Oil and Gas Service: Kuwait Oil Company Approach
Pressure vessels and piping conference

Authors: Al-Mithin, A.W., Al-Ahmad, A.W., Sardesai, V., Kumar, G.S.

Source: PROCEEDINGS OF THE ASME PRESSURE AND PIPING CONFERENCE. 7:141-148

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN078359776&indx=1&recIds=ETOCCN078359776

PVP2010-25423 Integrity Assessment of Pressure Vessels Subjected to Hydrogen Induced Damages
Pressure vessels and piping conference

Authors: Al-Mithin, A.W., Sardesai, V., Al-Ajmi, G., Hannan, A.S.A.

Source: PROCEEDINGS OF THE ASME PRESSURE AND PIPING CONFERENCE. 3:793-798

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN078356168&indx=1&recIds=ETOCCN078356168

Sacrificial Cathodic Protection (CP) System Inadequacy Due To 2-Phase Operation of 3-Phase Gas / Oil Separator
International petroleum technology

Authors: Al-Mithin, A.W., Sardesai, V., Sabri, H., Fernando, F.

Source: INTERNATIONAL PETROLEUM TECHNOLOGY CONFERENCE. 5:3398-3404

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN075463155&indx=1&recIds=ETOCCN075463155

Centranthera tranquebarica (Spreng.) Merr. (Orobanchaceae) - An Addition to the Flora of Maharashtra State

Authors: Sardesai, V. A., Kahalkar, V. I., Sathe, S. S., Shimpale, V. B.

Source: Journal of economic and taxonomic botany. 40(3/4):161-164

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCRN614334379&indx=1&recIds=ETOCRN614334379

Silicon Nitride Polish-Stop for CMP of BPSG Films on sub-0.25 mum DRAMs
Chemical mechanical planarization in IC device manufacturing

Authors: Stephens, J., Dobuzinsky, D., Gambino, J., Glashauser, W., Huckels, K., Hanebeck, J., Kraxenberger, M., Naeem, M., Rupp, T., Sardesai, V.

Source: PROCEEDINGS- ELECTROCHEMICAL SOCIETY PV. 37:234-238

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN036239712&indx=1&recIds=ETOCCN036239712

Rapid method for growth hormone receptor exon 3 delete (GHRd3) SNP genotyping from archival human placental samples

Authors: Pelekanos, R. A., Sardesai, V. S., Dekker Nitert, M., Callaway, L. K., Fisk, N. M., Jeffery, P. L.

Source: ENDOCRINE - BASINGSTOKE-. 49(3):643-652

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCRN372381319&indx=1&recIds=ETOCRN372381319