Design intent utilization for lithography compliance check and layout refinement to improve manufacturability

Authors: Kobayashi, Sachiko, Ikeuchi, Atsuhiko, Kimura, Kazunari, Kotani, Toshiya, Tanaka, Satoshi, Kyoh, Suigen, Maeda, Shimon, Inoue, Soichi

Source: 2011 e-Manufacturing & Design Collaboration Symposium & International Symposium on Semiconductor Manufacturing (eMDC & ISSM) Semiconductor Manufacturing (ISSM) and e-Manufacturing and Design Collaboration Symposium (eMDC), 2011 International Symposium on. :1-17 Sep, 2011

Relation: 2011 e-Manufacturing & Design Collaboration Symposium & International Symposium on Semiconductor Manufacturing (eMDC & ISSM)

The Photopolymer Science and Technology Award

Authors: Yoshimoto, Kenji, Yoshida, Akihisa, Ohshima, Masahiro, Taniguchi, Takashi, Kodera, Katsuyoshi, Naka, Yoshihiro, Kanai, Hideki, Kobayashi, Sachiko, Maeda, Shimon, Jiravanichsakul, Phubes

Source: Journal of photopolymer science and technology. 30(1):7-12

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCRN611967730&indx=1&recIds=ETOCRN611967730

Method for forming pattern and method for manufacturing semiconductor device

Pattern layout creation method, program product, and semiconductor device manufacturing method

METHOD OF OPTIMIZING SEMICONDUCTOR DEVICE MANUFACTURING PROCESS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

Pattern data creating method, pattern data creating program, and semiconductor device manufacturing method

Database creation method, database device and design data evaluation method

Pattern layout designing method, semiconductor device manufacturing method, and computer program product

MASK PATTERN GENERATING METHOD, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT

Method and program for pattern data generation using a modification guide

PATTERN LAYOUT CREATION METHOD, PROGRAM PRODUCT, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Method for verifying and correcting post-OPC pattern layout

PATTERN DATA CREATING METHOD, PATTERN DATA CREATING PROGRAM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

EVALUATION PATTERN GENERATING METHOD, COMPUTER PROGRAM PRODUCT, AND PATTERN VERIFYING METHOD

PATTERN CORRECTING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND PATTERN CORRECTING PROGRAM

METHOD AND CORRECTION APPARATUS FOR CORRECTING PROCESS PROXIMITY EFFECT AND COMPUTER PROGRAM PRODUCT

DATABASE CREATION METHOD, DATABASE DEVICE AND DESIGN DATA EVALUATION METHOD

DESIGN PATTERN CORRECTING METHOD, DESIGN PATTERN FORMING METHOD, PROCESS PROXIMITY EFFECT CORRECTING METHOD, SEMICONDUCTOR DEVICE AND DESIGN PATTERN CORRECTING PROGRAM

Pattern producing method, semiconductor device manufacturing method and program

PROCESS-MODEL GENERATION METHOD, COMPUTER PROGRAM PRODUCT, AND PATTERN CORRECTION METHOD