Extremely thin SOI for system-on-chip applications

Authors: Khakifirooz, A., Cheng, K., Liu, Q., Nagumo, T., Loubet, N., Reznicek, A., Kuss, J., Gimbert, J., Sreenivasan, R., Vinet, M., Grenouillet, L., Le Tiec, Y., Wacquez, R., Ren, Z., Cai, J., Shahrjerdi, D., Kulkarni, P., Ponoth, S., Luning, S., Doris, B.

Source: Proceedings of the IEEE 2012 Custom Integrated Circuits Conference Custom Integrated Circuits Conference (CICC), 2012 IEEE. :1-4 Sep, 2012

Relation: 2012 IEEE Custom Integrated Circuits Conference - CICC 2012

Advanced transistor structures for high performance microprocessors

Authors: Horstmann, M., Greenlaw, D., Feudel, T., Wei, A., Frohberg, K., Burbach, G., Gerhardt, M., Lenski, M., Stephan, R., Wieczorek, K., Schaller, M., Hohage, J., Ruelke, H., Klais, J., Huebler, P., Luning, S., van Bentum, R., Grasshoff, G., Schwan, C., Cheek, J., Buller, J., Krishnan, S., Raab, M., Kepler, N.

Source: 2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866) Integrated circuit design and technology Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on. :65-71 2004

Relation: 2004 International Conference on Integrated Circuit Design and Technology

Comparison of zero degree and tilted arsenic MDD implants

Authors: Tripsas, N.H., Nayak, D., Luning, S.

Source: Proceedings of 11th International Conference on Ion Implantation Technology Ion implantation technology Ion Implantation Technology. Proceedings of the 11th International Conference on. :33-36 1996

Relation: Proceedings of 11th International Conference on Ion Implantation Technology

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Authors: Yang, H.S., Malik, R., Narasimha, S., Li, Y., Divakaruni, R., Agnello, P., Allen, S., Antreasyan, A., Arnold, J.C., Bandy, K., Belyansky, M., Bonnoit, A., Bronner, G., Chan, V., Chen, X., Chen, Z., Chidambarrao, D., Chou, A., Clark, W., Crowder, S.W., Engel, B., Harifuchi, H., Huang, S.F., Jagannathan, R., Jamin, F.F., Kohyama, Y., Kuroda, H., Lai, C.W., Lee, H.K., Lee, W.-H., Lim, E.H., Lai, W., Mallikarjunan, A., Matsumoto, K., McKnight, A., Nayak, J., Ng, H.Y., Panda, S., Rengarajan, R., Steigerwalt, M., Subbanna, S., Subramanian, K., Sudijono, J., Sudo, G., Sun, S.-P., Tessier, B., Toyoshima, Y., Tran, P., Wise, R., Wong, R., Yang, I.Y., Wann, C.H., Su, L.T., Horstmann, M., Feudel, Th., Wei, A., Frohberg, K., Burbach, G., Gerhardt, M., Lenski, M., Stephan, R., Wieczorek, K., Schaller, M., Salz, H., Hohage, J., Ruelke, H., Klais, J., Huebler, P., Luning, S., van Bentum, R., Grasshoff, G., Schwan, C., Ehrichs, E., Goad, S., Buller, J., Krishnan, S., Greenlaw, D., Raab, M., Kepler, N.

Source: IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. Electron devices meeting Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International. :1075-1077 2004

Relation: 2004 International Electron Devices Meeting

Kinetics of high concentration arsenic deactivation at moderate to low temperatures

Authors: Luning, S., Rousseau, P.M., Griffin, P.B., Carey, P.G., Plummer, J.D.

Source: 1992 International Technical Digest on Electron Devices Meeting Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International. :457-460 1992

Relation: Proceedings of IEEE International Electron Devices Meeting

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper

Authors: Greene, B., Liang, Q., Amarnath, K., Wang, Y., Schaeffer, J., Cai, M., Liang, Y., Saroop, S., Cheng, J., Rotondaro, A., Han, S.-J., Mo, R., McStay, K., Ku, S., Pal, R., Kumar, M., Dirahoui, B., Yang, B., Tamweber, F., Lee, W.-H., Steigerwalt, M., Weijtmans, H., Holt, J., Black, L., Samavedam, S., Turner, M., Ramani, K., Lee, D., Belyansky, M., Chowdhury, M., Aime, D., Min, B., van Meer, H., Yin, H., Chan, K., Angyal, M., Zaleski, M., Ogunsola, O., Child, C., Zhuang, L., Yan, H., Permanaa, D., Sleight, J., Guo, D., Mittl, S., Ioannou, D., Wu, E., Chudzik, M., Park, D.-G., Brown, D., Luning, S., Mocuta, D., Maciejewski, E., Henson, K., Leobandung, E.

Source: 2009 Symposium on VLSI Technology VLSI Technology, 2009 Symposium on. :140-141 Jun, 2009

Relation: 2009 Symposium on VLSI Technology

High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor

Authors: Yang, B., Takalkar, R., Ren, Z., Black, L., Dube, A., Weijtmans, J.W., Li, J., Johnson, J.B., Faltermeier, J., Madan, A., Zhu, Z., Turansky, A., Xia, G., Chakravarti, A., Pal, R., Chan, K., Reznicek, A., Adam, T.N., de Souza, J.P., Harley, E.C.T., Greene, B., Gehring, A., Cai, M., Aime, D., Sun, S., Meer, H., Holt, J., Theodore, D., Zollner, S., Grudowski, P., Sadana, D., Park, D.-G., Mocuta, D., Schepis, D., Maciejewski, E., Luning, S., Pellerin, J., Leobandung, E.

Source: 2008 IEEE International Electron Devices Meeting Electron Devices Meeting, 2008. IEDM 2008. IEEE International. :1-4 Dec, 2008

Relation: 2008 IEEE International Electron Devices Meeting (IEDM)

Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing

Authors: Cai, M., Greene, B. J., Strane, J., Belyansky, M., Tamweber, F., Lee, D., van Meer, H., Laffosse, E., Luning, S., Mocuta, D., Maciejewski, E.

Source: 2008 IEEE International SOI Conference SOI Conference, 2008. SOI. IEEE International. :17-18 Oct, 2008

Relation: 2008 IEEE International SOI Conference

(110) channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (Rext) engineering

Authors: Yang, B., Waite, A., Yin, H., Yu, J., Black, L., Chidambarrao, D., Domenicucci, A., Wang, X., Ku, S. H., Wang, Y., Meer, H. V., Kim, B., Nayfeh, H., Kim, S.D., Tabakman, K., Pal, R., Nummy, K., Greene, B., Fisher, P., Liu, J., Liang, Q., Holt, J., Narasimha, S., Luo, Z., Utomo, H., Chen, X., Park, D., Sung, C.Y., Wachnik, R., Freeman, G., Schepis, D., Maciejewski, E., Khare, M., Leobandung, E., Luning, S., Agnello, P.

Source: 2007 IEEE International Electron Devices Meeting Electron Devices Meeting, 2007. IEDM 2007. IEEE International. :1032-1034 Dec, 2007

Relation: 2007 IEEE International Electron Devices Meeting

Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current

Authors: Yang, B., Nummy, K., Waite, A., Black, L., Gossmann, H., Yin, H., Liu, Y., Kim, B., Narasimha, S., Fisher, P., Meer, H. V., Johnson, J., Chidambarrao, D., Kim, S.D., Sheraw, C., Wehella-gamage, D., Holt, J., Chen, X., Park, D., Sung, C.Y., Schepis, D., Khare, M., Luning, S., Agnello, P.

Source: 2007 IEEE Symposium on VLSI Technology VLSI Technology, 2007 IEEE Symposium on. :126-127 Jun, 2007

Relation: 2007 IEEE Symposium on VLSI Technology

CMOS Fabricated by Hybrid-Orientation Technology (HOT)

Authors: Yang, Bin, Yang, M., Fried, D. M., Sheraw, C. D., Waite, A., Nummy, K., Black, L., Kim, S. D., Yin, H., Kim, B., Narasimha, S., Chen, X., Khare, M., Luning, S., Agnello, P.

Source: 2007 International Workshop on Electron Devices and Semiconductor Technology (EDST) Electron Devices and Semiconductor Technology, 2007. EDST 2007. Proceeding of 2007 International Workshop on. :8-13 Jun, 2007

Relation: 2007 International Workshop on Electron Devices and Semiconductor Technology

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

Authors: Agnello, P., Ivers, T., Warm, C., Wise, R., Wachnik, R., Schepis, D., Sankaran, S., Norum, J., Luning, S., Li, Y., Khare, M., Grill, A., Edelstein, D., Chen, X., Brown, D., Augur, R., Wu, S., Yu, J., Wong, R.C., Werking, J., Wehella-Gamage, D., Vayshenker, A., Van Meer, H., Van Den Nieuwenhuizen, R., Tian, C., Tabakman, K., Sung, C.Y., Standaert, T., Simon, A., Sim, J., Sheraw, C., Restaino, D., Rausch, W., Pal, R., Prindle, C., Ouyang, X., Ouyang, C., Ontalus, V., Nummy, K., Nielsen, D., Nicholson, L., McKnight, A., Lustig, N., Liu, X., Lee, M.H., Lea, D., Larosa, G., Landers, W., Kim, B., Kelling, M., Jeng, S.-J., Holt, J., Hargrove, M., Grunow, S., Greco, S., Gates, S., Frye, A., Fisher, P., Domenicucci, A., Dimitrakopoulos, C., Costrini, G., Chou, A., Cheng, J., Butt, S., Black, L., Belyansky, M., Ahsan, I., Adam, T., Gabor, A., Wu, C.-H.J., Yang, D., Crouse, M., Robinson, C., Corliss, D., Fonseca, C., Johnson, J., Weybright, M., Waite, A., Nayfeh, H.M., Onishi, K., Narasimha, S.

Source: 2006 International Electron Devices Meeting Electron Devices Meeting, 2006. IEDM '06. International. :1-4 Dec, 2006

Relation: 2006 International Electron Devices Meeting

High Performance 65nm SOI Transistors Using Laser Spike Annealing

Authors: Tenko Yamashita, Fisher, P.A., Gluschenkov, O., Hideki Kimura, Ramachandran, R., Mocuta, A.C., Kluth, J., Takahiro Kawamura, Katsunori Onishi, Fried, D., Narasimha, S., Brown, D., Jain, S., Koji Miyamoto, Freeman, G., Deshpande, S.V., Luning, S., Shih-Fen Huang, Pellerin, J., Hideaki Kuroda

Source: 2006 European Solid-State Device Research Conference Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European. :347-350 Sep, 2006

Relation: 2006 European Solid-State Device Research Conference

Ground plane optimization for 20nm FDSOI transistors with thin Buried Oxide

Authors: Grenouillet, L., Khare, P., Gimbert, J., Hargrove, M., Jaud, M. A., Liu, Q., Le Tiec, Y., Wacquez, R., Loubet, N., Cheng, K., Holmes, S., Liu, S., Hook, T., Teehan, S., Guilford, J., Schmitz, S., Kulkarni, P., Kuss, J., Terrizzi, M., Luning, S., Doris, B., Vinet, M.

Source: 2012 IEEE International SOI Conference (SOI) SOI Conference (SOI), 2012 IEEE International. :1-2 Oct, 2012

Relation: 2012 IEEE International SOI Conference

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

Authors: Khakifirooz, A., Cheng, K., Nagumo, T., Loubet, N., Adam, T., Reznicek, A., Kuss, J., Shahrjerdi, D., Sreenivasan, R., Ponoth, S., He, H., Kulkarni, P., Liu, Q., Hashemi, P., Khare, P., Luning, S., Mehta, S., Gimbert, J., Zhu, Y., Zhu, Z., Li, J., Madan, A., Levin, T., Monsieur, F., Yamamoto, T., Naczas, S., Schmitz, S., Holmes, S., Aulnette, C., Daval, N., Schwarzenbach, W., Nguyen, B.-Y., Paruchuri, V., Khare, M., Shahidi, G., Doris, B.

Source: 2012 Symposium on VLSI Technology (VLSIT) VLSI Technology (VLSIT), 2012 Symposium on. :117-118 Jun, 2012

Relation: 2012 IEEE Symposium on VLSI Technology

Implant approaches and challenges for 20nm node and beyond ETSOI devices

Authors: Ponoth, S., Vinet, M., Grenouillet, L., Kumar, A., Kulkarni, P., Liu, Q., Cheng, K., Haran, B., Posseme, N., Khakifirooz, A., Loubet, N., Mehta, S., Kuss, J., Destefanis, V., Berliner, N., Sreenivasan, R., Le Tiec, Y., Kanakasabapathy, S., Schmitz, S., Levin, T., Luning, S., Hook, T., Khare, M., Shahidi, G., Doris, B.

Source: IEEE 2011 International SOI Conference SOI Conference (SOI), 2011 IEEE International. :1-2 Oct, 2011

Relation: 2011 IEEE International SOI Conference

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

Authors: Cheng, K., Khakifirooz, A., Kulkarni, P., Ponoth, S., Haran, B., Kumar, A., Adam, T., Reznicek, A., Loubet, N., He, H., Kuss, J., Wang, M., Levin, T. M., Monsieur, F., Liu, Q., Sreenivasan, R., Cai, J., Kimball, A., Mehta, S., Luning, S., Zhu, Y., Zhu, Z., Yamamoto, T., Bryant, A., Lin, C. -H., Naczas, S., Jagannathan, H., Edge, L. F., Allegret-Maret, S., Dube, A., Kanakasabapathy, S., Schmitz, S., Inada, A., Seo, S., Raymond, M., Zhang, Z., Yagishita, A., Demarest, J., Li, J., Hopstaken, M., Berliner, N., Upham, A., Johnson, R., Holmes, S., Standaert, T., Smalley, M., Zamdmer, N., Ren, Z., Wu, T., Bu, H., Paruchuri, V., Sadana, D., Narayanan, V., Haensch, W., O'Neill, J., Hook, T., Khare, M., Doris, B.

Source: 2011 Symposium on VLSI Technology - Digest of Technical Papers VLSI Technology (VLSIT), 2011 Symposium on. :128-129 Jun, 2011

Relation: 2011 IEEE Symposium on VLSI Technology

Impact of back bias on ultra-thin body and BOX (UTBB) devices

Authors: Liu, Q., Monsieur, F., Kumar, A., Yamamoto, T., Yagishita, A., Kulkarni, P., Ponoth, S., Loubet, N., Cheng, K., Khakifirooz, A., Haran, B., Vinet, M., Cai, J., Kuss, J., Linder, B., Grenouillet, L., Mehta, S., Khare, P., Berliner, N., Levin, T., Kanakasabapathy, S., Upham, A., Sreenivasan, R., Le Tiec, Y., Posseme, N., Li, J., Demarest, J., Smalley, M., Leobandung, E., Monfray, S., Boeuf, F., Skotnicki, T., Ishimaru, K., Takayanagi, M., Kleemeier, W., Bu, H., Luning, S., Hook, T., Khare, M., Shahidi, G., Doris, B., Sampson, R.

Source: 2011 Symposium on VLSI Technology - Digest of Technical Papers VLSI Technology (VLSIT), 2011 Symposium on. :160-161 Jun, 2011

Relation: 2011 IEEE Symposium on VLSI Technology

Dual stress liner enhancement in hybrid orientation technology

Authors: Sheraw, C.D., Yang, M., Fried, D.M., Costrini, G., Kanarsky, T., Lee, W.-H., Chan, V., Fischetti, M.V., Holt, J., Black, L., Naeem, M., Panda, S., Economikos, L., Groschopf, J., Kapur, A., Li, Y., Mo, R.T., Bonnoit, A., Degraw, D., Luning, S., Chidambarrao, D., Wang, X., Bryant, A., Brown, D., Sung, C.-Y., Agnello, P., Ieong, M., Huang, S.-F., Chen, X., Khare, M.

Source: Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. VLSI Technology VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on. :12-13 2005

Relation: 2005 Symposium on VLSI Technology

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

Authors: Liu, Q., Vinet, M., Gimbert, J., Loubet, N., Wacquez, R., Grenouillet, L., Le Tiec, Y., Khakifirooz, A., Nagumo, T., Cheng, K., Kothari, H., Chanemougame, D., Chafik, F., Guillaumet, S., Kuss, J., Allibert, F., Tsutsui, G., Li, J., Morin, P., Mehta, S., Johnson, R., Edge, L. F., Ponoth, S., Levin, T., Kanakasabapathy, S., Haran, B., Bu, H., Bataillon, J.-L., Weber, O., Faynot, O., Josse, E., Haond, M., Kleemeier, W., Khare, M., Skotnicki, T., Luning, S., Doris, B., Celik, M., Sampson, R.

Source: 2013 IEEE International Electron Devices Meeting Electron Devices Meeting (IEDM), 2013 IEEE International. :9.2.1-9.2.4 Dec, 2013

Relation: 2013 IEEE International Electron Devices Meeting (IEDM)