29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme

Authors: Fujiwara, Hidehiro, Zhao, Wei-Chang, Khare, Kinshuk, Nien, Yi-Hsin, Lin, Chih-Yu, Lin, Cheng-Han, Liao, Shan-Ru, Torigoe, Kenta, Xia, Shirleen, Ishii, Yuichiro, Lin, Yao-Yi, Liaw, Jhon-Jhy, Chen, Yen-Huei, Liao, Hung-Jen, Chang, Tsung-Yung Jonathan

Source: 2025 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2025 IEEE International. 68:500-502 Feb, 2025

Relation: 2025 IEEE International Solid-State Circuits Conference (ISSCC)