A SAR ADC missing-decision level detection and removal technique

Authors: Huang, Jiun-Lang, Huang, X.-L., Chou, Y.-F., Kwai, D.-M.

Source: 2012 IEEE 30th VLSI Test Symposium (VTS) VLSI Test Symposium (VTS), 2012 IEEE 30th. :31-36 Apr, 2012

Relation: 2012 IEEE 30th VLSI Test Symposium (VTS)

Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults

Authors: Peng, Y.-L., Kwai, D.-M., Chou, Y.-F., Wu, C.-W.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 22(2):207-219 Feb, 2014

Implementation of memory stacking on logic controller by using 3DIC 300mm backside TSV process integration

Authors: Chen, S.-C., Tzeng, P.-J., Hsm, Y.-C., Wang, C.-C., Chang, P.-C., Chen, J.-C., Chang, Y.-H., Chen, T.-S., Hsu, T.-C., Chang, H.-H., Zhan, C.-J., Lee, C.-H., Chou, Y.-F., Kwai, D.-M., Ku, T.-K., Wang, P.-H., Lo, W.-C.

Source: 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) VLSI Technology, Systems and Application (VLSI-TSA), 2016 International Symposium on. :1-2 Apr, 2016

Relation: 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs

Authors: Chou, Y.-F., Kwai, D.-M., Shieh, M.-D., Wu, C.-W.

Source: IEEE Transactions on Circuits and Systems I: Regular Papers IEEE Trans. Circuits Syst. I Circuits and Systems I: Regular Papers, IEEE Transactions on. 60(9):2343-2351 Sep, 2013

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis

Authors: Lin, Y.-H., Huang, S.-Y., Tsai, K.-H., Cheng, W.-T., Sunter, S., Chou, Y.-F., Kwai, D.-M.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 32(5):737-747 May, 2013

Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism

Authors: Ke, J.-W., Huang, S.-Y., Tzeng, C.-W., Kwai, D.-M., Chou, Y.-F.

Source: IEEE Transactions on Circuits and Systems I: Regular Papers IEEE Trans. Circuits Syst. I Circuits and Systems I: Regular Papers, IEEE Transactions on. 60(4):908-917 Apr, 2013

In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis

Authors: You, J.-W., Huang, S.-Y., Lin, Y.-H., Tsai, M.-H., Kwai, D.-M., Chou, Y.-F., Wu, C.-W.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 21(3):443-453 Mar, 2013

Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers

Authors: Chang, H.-M., Huang, J.-L., Kwai, D.-M., Cheng, K.-T., Wu, C.-W.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 21(3):465-474 Mar, 2013

Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias

Authors: Chou, Y.-F., Kwai, D.-M., Wu, C.-W.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 19(8):1346-1356 Aug, 2011

Periodically regular chordal rings: generality, scalability, and VLSI layout

Authors: Kwai, D.-M., Parhami, B.

Source: Proceedings of SPDP '96: 8th IEEE Symposium on Parallel and Distributed Processing Parallel and distributed processing Parallel and Distributed Processing, 1996., Eighth IEEE Symposium on. :148-151 1996

Relation: Proceedings of SPDP '96: 8th IEEE Symposium on Parallel and Distributed Processing

Benchmarking for Research in Power Delivery Networks of Three-Dimensional Integrated Circuits
Physical design

Authors: Luo, P.-W., Zhang, C., Chang, Y.-T., Cheng, L.-C., Lee, H.-H., Sheu, B.-L., Su, Y.-S., Kwai, D.-M., Shi, Y.

Source: INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN. :17-24

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN085794497&indx=1&recIds=ETOCCN085794497

Small Delay Testing for TSVs in 3-D ICs
Design automation conference; 2012 49th ACM/EDAC/IEEE design automation conference

Authors: Lin, Y.-H., Huang, S.-Y., Tsai, K.-H., Cheng, W.-T., Sunter, S., Chou, Y.-F., Kwai, D.-M.

Source: DESIGN AUTOMATION CONFERENCE. 2:1031-1036

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN082495755&indx=1&recIds=ETOCCN082495755

Thermal-Aware On-Line Task Allocation for 3D Multi-Core Processor Throughput Optimization
Design, automation and test in Europe

Authors: Lung, C.-L., Ho, Y.-L., Kwai, D.-M., Chang, S.-C.

Source: DATE -PROCEEDINGS- HARDCOPY-. (1):8-13

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN080213395&indx=1&recIds=ETOCCN080213395

Floorplanning 1024 Cores in a 3D-Stacked Network-on-Chip with Thermal-Aware Redistribution
Thermal and thermomechanical phenomena in electronic systems

Authors: Chien, J.-H., Lung, C.-L., Hsu, C.-C., Chou, Y.-F., Kwai, D.-M.

Source: I THERM. 2:721-726

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN076699640&indx=1&recIds=ETOCCN076699640

Measurement and Characterization of 6T SRAM Cell Current
IEEE international workshop on memory technology, design and testing

Authors: Hsiao, C.-H., Kwai, D.-M.

Source: RECORDS OF THE IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING. :140-145

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN057755815&indx=1&recIds=ETOCCN057755815

Via-Programmable Read-Only Memory Design for Full Code Coverage Using a Dynamic Bit-Line Shielding Technique
IEEE international workshop on memory technology, design and testing

Authors: Chang, M.-F., Kwai, D.-M., Wen, K.-A.

Source: RECORDS OF THE IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING. :16-21

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN057755610&indx=1&recIds=ETOCCN057755610

Characterization and Generalization of Honeycomb and Diamond Networks
Parallel and distributed processing techniques and applications

Authors: Kwai, D.-M., Parhami, B.

Source: PDPTA -INTERNATIONAL CONFERENCE-. :2947-2952

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN040904438&indx=1&recIds=ETOCCN040904438

Challenges in Interconnection Network Design in the Era of Multiprocessor and Massively Parallel Microchips
Communications in computing; CIC '2000

Authors: Parhami, B., Kwai, D.-M.

Source: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON COMMUNICATIONS IN COMPUTING. :241-246

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN039295350&indx=1&recIds=ETOCCN039295350

Detection of SRAM Cell Stability by Lowering Array Supply Voltage
Asian test symposium

Authors: Kwai, D.-M., Chang, H.-W., Liao, H.-J., Chiao, C.-H., Chou, Y.-F.

Source: PROCEEDINGS OF THE ASIAN TEST SYMPOSIUM. :268-273

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN037531844&indx=1&recIds=ETOCCN037531844

High-Performance Array Processing with Fully Pipelined Data Streams and Control Paths
Parallel and distributed computing and systems

Authors: Kwai, D.-M., Parhami, B.

Source: PARALLEL AND DISTRIBUTED COMPUTING AND SYSTEMS. 2:609-612

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN050468902&indx=1&recIds=ETOCCN050468902