New Energy Transformation Model for the Unclamped Inductive Switching (UIS) Test

Authors: Lee, J.-H., Nidhi, K., Chen, C.-C., Ker, M.-D.

Source: 2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Physical and Failure Analysis of Integrated Circuits (IPFA), 2020 IEEE International Symposium on the. :1-7 Jul, 2020

Relation: 2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

Comprehensive Investigations of HBM ESD Robustness for GaN-on-Si RF HEMTs

Authors: Abhinay, S., Wu, W.-M., Shih, C.-A., Chen, S.-H., Sibaja-Hernandez, A., Parvais, B., Peralagu, U., Alian, A., Wu, T.-L., Ker, M.-D., Groeseneken, G., Collaert, N.

Source: 2022 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2022 International. :30.7.1-30.7.4 Dec, 2022

Relation: 2022 IEEE International Electron Devices Meeting (IEDM)

ESD HBM Discharge Model in RF GaN-on-Si (MIS)HEMTs

Authors: Wu, W.-M., Chen, S.-H., Sibaja-Hernandez, A., Yadav, S., Peralagu, U., Yu, H., Alian, A., Putcha, V., Parvais, B., Groeseneken, G., Ker, M.-D., Collaert, N.

Source: 2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :39.5.1-39.5.4 Dec, 2021

Relation: 2021 IEEE International Electron Devices Meeting (IEDM)

A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

Authors: Luo, Z., Ker, M.-D.

Source: IEEE Transactions on Biomedical Circuits and Systems IEEE Trans. Biomed. Circuits Syst. Biomedical Circuits and Systems, IEEE Transactions on. 10(6):1087-1099 Dec, 2016

Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits

Authors: Tsai, H.-W., Ker, M.-D.

Source: IEEE Transactions on Device and Materials Reliability IEEE Trans. Device Mater. Relib. Device and Materials Reliability, IEEE Transactions on. 14(1):493-498 Mar, 2014

On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology

Authors: Ker, M.-D., Yeh, C.-T.

Source: IEEE Transactions on Device and Materials Reliability IEEE Trans. Device Mater. Relib. Device and Materials Reliability, IEEE Transactions on. 14(1):536-544 Mar, 2014

A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control

Authors: Chen, W.-M., Chiueh, H., Chen, T.-J., Ho, C.-L., Jeng, C., Ker, M.-D., Lin, C.-Y., Huang, Y.-C., Chou, C.-W., Fan, T.-Y., Cheng, M.-S., Hsin, Y.-L., Liang, S.-F., Wang, Y.-L., Shaw, F.-Z., Huang, Y.-H., Yang, C.-H., Wu, C.-Y.

Source: IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 49(1):232-247 Jan, 2014

Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process

Authors: Lin, C.-Y., Chu, L.-W., Ker, M.-D.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 60(11):3625-3631 Nov, 2013

Design of $2 \times {\rm V}_{\rm DD}$-Tolerant I/O Buffer With PVT Compensation Realized by Only $1 \times {\rm V}_{\rm DD}$ Thin-Oxide Devices

Authors: Ker, M.-D., Chiu, P.-Y.

Source: IEEE Transactions on Circuits and Systems I: Regular Papers IEEE Trans. Circuits Syst. I Circuits and Systems I: Regular Papers, IEEE Transactions on. 60(10):2549-2560 Oct, 2013

Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process

Authors: Altolaguirre, F. A., Ker, M.-D.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 60(10):3500-3507 Oct, 2013

Implantable Stimulator for Epileptic Seizure Suppression With Loading Impedance Adaptability

Authors: Lin, C.-Y., Chen, W.-L., Ker, M.-D.

Source: IEEE Transactions on Biomedical Circuits and Systems IEEE Trans. Biomed. Circuits Syst. Biomedical Circuits and Systems, IEEE Transactions on. 7(2):196-203 Apr, 2013

Design of Dual-Band ESD Protection for 24-/60-GHz Millimeter-Wave Circuits

Authors: Chu, L.-W., Lin, C.-Y., Ker, M.-D.

Source: IEEE Transactions on Device and Materials Reliability IEEE Trans. Device Mater. Relib. Device and Materials Reliability, IEEE Transactions on. 13(1):110-118 Mar, 2013

High Area-Efficient ESD Clamp Circuit With Equivalent $RC$-Based Detection Mechanism in a 65-nm CMOS Process

Authors: Yeh, C.-T., Ker, M.-D.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 60(3):1011-1018 Mar, 2013

Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process

Authors: Lin, C.-Y., Tsai, S.-Y., Chu, L.-W., Ker, M.-D.

Source: IEEE Transactions on Microwave Theory and Techniques IEEE Trans. Microwave Theory Techn. Microwave Theory and Techniques, IEEE Transactions on. 61(2):914-921 Feb, 2013

Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology

Authors: Yeh, C.-T., Ker, M.-D.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 59(12):3456-3463 Dec, 2012

Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology

Authors: Yeh, C.-T., Ker, M.-D.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 59(10):2626-2634 Oct, 2012

Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology

Authors: Lin, C.-Y., Chu, L.-W., Tsai, S.-Y., Ker, M.-D.

Source: IEEE Transactions on Device and Materials Reliability IEEE Trans. Device Mater. Relib. Device and Materials Reliability, IEEE Transactions on. 12(3):554-561 Sep, 2012

Characterization of SOA in Time Domain and the Improvement Techniques for Using in High-Voltage Integrated Circuits

Authors: Chen, W.-Y., Ker, M.-D.

Source: IEEE Transactions on Device and Materials Reliability IEEE Trans. Device Mater. Relib. Device and Materials Reliability, IEEE Transactions on. 12(2):382-390 Jun, 2012

ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process

Authors: Lin, C.-Y., Chu, L.-W., Ker, M.-D.

Source: IEEE Transactions on Microwave Theory and Techniques IEEE Trans. Microwave Theory Techn. Microwave Theory and Techniques, IEEE Transactions on. 60(3):714-723 Mar, 2012

New Design of 2 $\times$ VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology

Authors: Yeh, C.-T., Ker, M.-D.

Source: IEEE Transactions on Circuits and Systems II: Express Briefs IEEE Trans. Circuits Syst. II Circuits and Systems II: Express Briefs, IEEE Transactions on. 59(3):178-182 Mar, 2012