ESD Robustness of Germanium Photodetectors in Advanced Silicon Photonics Technology

Authors: Chen, Shih-Hung, Fu, P.-Y., Tsiara, A., Van De Peer, M., Simicic, M., Musibau, S., Ban, Y., Kao, K.-H., Chen, W.-C., Serbulova, K., Van Campenhout, J., Absil, Ph., Croes, K.

Source: 2024 46th Annual EOS/ESD Symposium (EOS/ESD) EOS/ESD Symposium (EOS/ESD), 2024 46th Annual. 46:1-7 Sep, 2024

Relation: 2024 46th Annual EOS/ESD Symposium (EOS/ESD)

First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure

Authors: Yu, X.-R., Hsieh, C.-C., Chuang, M.-H., Chiu, M.-Y., Sun, T.-C., Geng, W.-Z., Chang, W.-H., Shih, Y.-J., Lu, W.-H., Chang, W.-C., Lin, Y.-C., Pai, Y.-C., Lai, C.-Y., Dei, Y., Yang, C.-Y., Lu, H.-Y., Lin, N.-C., Wu, C.-T., Kao, K.-H., Ma, W. C.-Y., Lu, D. D., Lee, Y.-J., Luo, G.-L., Chiang, M.-H., Maeda, T., Wu, W.-F., Li, Y.-M., Hou, T.-H.

Source: 2023 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2023 International. :1-4 Dec, 2023

Relation: 2023 International Electron Devices Meeting (IEDM)

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization

Authors: Lin, W.-C., Huang, H.-P., Kao, K.-H., Chiang, M.-H., Lu, D., Hsu, W.-C., Wang, Y.-H., Ma, W.C.-Y., Tsai, H.-H., Lee, Y.-J., Chiang, H.-L., Wang, J.-F., Radu, I.

Source: ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC) Solid-State Device Research Conference (ESSDERC), ESSDERC 2023 - IEEE 53rd European. :9-12 Sep, 2023

Relation: ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC)

How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology

Authors: Chiang, H.-L., Hadi, R. A., Wang, J.-F., Han, H.-C., Wu, J.-J., Hsieh, H.-H., Horng, J.-J., Chou, W.-S., Lien, B.-S., Chang, C.-H., Chen, Y.-C., Wang, Y.-H., Chen, T.-C., Liu, J.-C., Liu, Y.-C., Chiang, M.-H., Kao, K.-H., Pulicherla, B., Cai, J., Chang, C.-S., Su, K.-W., Cheng, K.-L., Yeh, T.-J., Peng, Y.-C., Enz, C., Chang, M.-C. F., Chang, M.-F., Wong, H.-S. P., Radu, I. P.

Source: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2023 IEEE Symposium on. :1-2 Jun, 2023

Relation: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering

Authors: Yu, X.-R., Chang, W.-H, Hong, T.-C., Sung, P.-J., Agarwal, A., Luo, G.-L., Wu, C.-T., Kao, K.-H., Su, C.-J., Chang, S.-W., Lu, W.-H., Fu, P.-Y., Lin, J.-H., Wu, P.-H., Cho, T.-C., Ma, W. C.-Yu., Lu, D.-D., Chao, T.-S., Maeda, T., Lee, Y.-J., Wu, W.-F., Yeh, W.-K., Wang, Y.-H.

Source: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2022 IEEE Symposium on. :399-400 Jun, 2022

Relation: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

First Demonstration of Heterogeneous L-shaped Field Effect Transistor (LFET) for Angstrom Technology Nodes

Authors: Yang, C.-Y., Sung, P.-J., Chuang, M.-H., Chang, C.-W., Shih, Y.-J., Huang, T.-Y., Lu, D. D., Hong, T.-C., Yu, X.-R., Lu, W.-H., Chang, S.-W., Tsai, J.-J., Huang, M.-K., Cho, T.-C., Lee, Y.-J., Luo, K.-L., Wu, C.-T., Su, C.-J., Kao, K.-H., Chao, T.-S., Wu, W.-F., Wang, Y.-H.

Source: 2022 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2022 International. :20.2.1-20.2.4 Dec, 2022

Relation: 2022 IEEE International Electron Devices Meeting (IEDM)

Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size

Authors: Yu, X.-R., Chuang, M.-H., Chang, S.-W., Chang, W.-H., Hong, T.-C., Chiang, C.-H., Lu, W.-H., Yang, C.-Y., Chen, W.-J., Lin, J.-H., Wu, P.-H., Sun, T.-C., Kola, S., Yang, Y.-S., Da, Yun, Sung, P.-J., Wu, C.-T., Cho, T.-C., Luo, G.-L., Kao, K.-H., Chiang, M.-H., Ma, W. C.-Y., Su, C.-J., Chao, T.-S., Maeda, T., Samukawa, S., Li, Y., Lee, Y.-J., Wu, W.-F., Tarng, J.-H., Wang, Y.-H.

Source: 2022 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2022 International. :20.5.1-20.5.4 Dec, 2022

Relation: 2022 IEEE International Electron Devices Meeting (IEDM)

First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications

Authors: Chang, S.-W., Lu, T.-H., Yang, C.-Y., Yeh, C.-J., Huang, M.-K., Meng, C.-F., Chen, P.-J., Chang, T.-H., Chang, Y.-S., Jhu, J.-W., Hong, T.-Z., Ke, C.-C., Yu, X.-R., Lu, W.-H., Baig, M. A., Cho, T.-C., Sung, P.-J., Su, C.-J., Hsueh, F.-K., Chen, B.-Y., Hu, H.-H., Wu, C.-T., Lin, K.-L., Ma, W. C.-Y., Lu, D.-D., Kao, K.-H., Lee, Y.-J., Lin, C.-L., Huang, K.-P., Chen, K.-M., Li, Y., Samukawa, S., Chao, T.-S., Huang, G.-W., Wu, W.-F., Lee, W.-H., Li, J.-Y., Shieh, J.-M., Tarng, J.-H., Wang, Y.-H., Yeh, W.-K.

Source: 2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :34.4.1-34.4.4 Dec, 2021

Relation: 2021 IEEE International Electron Devices Meeting (IEDM)

3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers

Authors: Su, C. J., Huang, M. K., Lee, K. S., Hu, V. P. H., Huang, Y. F., Zheng, B. C., Yao, C. H., Lin, N. C., Kao, K. H., Hong, T. C., Sung, P. J., Wu, C. T., Yu, T. Y., Lin, K. L., Tseng, Y. C., Lin, C. L., Lee, Y. J., Chao, T. S., Li, J. Y., Wu, W. F., Shieh, J. M., Wang, Y. H., Yeh, W. K.

Source: 2020 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2020 IEEE International. :12.2.1-12.2.4 Dec, 2020

Relation: 2020 IEEE International Electron Devices Meeting (IEDM)

First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)

Authors: Hong, T.-Z., Chang, W.-H., Agarwal, A., Huang, Y.-T., Yang, C.-Y., Chu, T.-Y., Chao, H.-Y., Chuang, Y., Chung, S.-T., Lin, J.-H., Luo, S.-M., Tsai, C.-J., Li, M.-J., Yu, X.-R., Lin, N.-C., Cho, T.-C., Sung, P.-J., Su, C.-J., Luo, G.-L., Hsueh, F.-K., Lin, K.-L., Ishii, H., Irisawa, T., Maeda, T., Wu, C.-T., Ma, W. C.-Y., Lu, D.-D., Kao, K.-H., Lee, Y.-J., Chen, H. J.-H., Lin, C.-L., Chuang, R. W., Huang, K.-P., Samukawa, S., Li, Y.-M., Tarng, J.-H., Chao, T.-S., Miura, M., Huang, G.-W., Wu, W.-F., Li, J.-Y., Shieh, J.-M., Wang, Y.-H., Yeh, W.-K.

Source: 2020 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2020 IEEE International. :15.5.1-15.5.4 Dec, 2020

Relation: 2020 IEEE International Electron Devices Meeting (IEDM)

A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs

Authors: Tang, Y.-T, Fan, C.-L., Kao, Y.-C., Modolo, N., Su, C.-J., Wu, T.-L., Kao, K.-H., Wu, P.-J., Hsaio, S.-W., Useinov, A., Su, Pin, Wu, W.-F., Huang, G.-W., Shieh, J.-M., Yeh, W.-K., Wang, Y.-H.

Source: 2019 Symposium on VLSI Technology VLSI Technology, 2019 Symposium on. :T222-T223 Jun, 2019

Relation: 2019 Symposium on VLSI Technology

Fabrication of $\Omega$ -gated Negative Capacitance FinFETs and SRAM

Authors: Sung, P.-J., Su, C.-J., Lu, D. D., Luo, S.-X., Kao, K.-H., Ciou, J.-Y., Jao, C.-Y., Hsu, H.-S., Wang, C.-J., Hong, T.-C., Liao, T.-H., Fang, C.-C., Wang, Y.-S., Huang, H.-F., Li, J.-H., Huang, Y.-C., Hsueh, F.-K., Wu, C.-T., Ma, W. C.-Y., Huang, K.-P., Lee, Y.-J., Chao, T.-S., Li, J.-Y., Wu, W.-F., Yeh, W.-K., Wang, Y.-H.

Source: 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) VLSI Technology, Systems and Application (VLSI-TSA), 2019 International Symposium on. :1-2 Apr, 2019

Relation: 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node

Authors: Tang, Y.-T, Su, C.-J., Wang, Y.-S., Kao, K.-H., Wu, T.-L., Sung, P.-J., Hou, F.-J., Wang, C.-J., Yeh, M.-S., Lee, Y.-J., Wu, W.-F., Huang, G.-W., Shieh, J.-M., Yeh, W.-K., Wang, Y.-H.

Source: 2018 IEEE Symposium on VLSI Technology VLSI Technology, 2018 IEEE Symposium on. :45-46 Jun, 2018

Relation: 2018 IEEE Symposium on VLSI Technology

First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

Authors: Chang, S.-W., Sung, P.-J., Chu, T-Y., Lu, D. D., Wang, C.-J., Lin, N.-C., Su, C.-J., Lo, S.-H., Huang, H.-F., Li, J.-H., Huang, M.-K., Huang, Y.-C., Huang, S.-T., Wang, H.-C., Huang, Y.-J., Wang, J.-Y., Yu, L. - W, Huang, Y.-F., Hsueh, F. - K., Wu, C.-T., Ma, W. C.-Y., Kao, K.-H., Lee, Y. - J., Lin, C.-L., Chuang, R. W., Huang, K.-P., Samukawa, S., Li, Y., Lee, W. - H., Chao, T.-S., Huang, G. - W., Wu, W.-F., Li, J. - Y., Shieh, J.-M., Yeh, W. - K., Wang, Y.-H.

Source: 2019 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2019 IEEE International. :11.7.1-11.7.4 Dec, 2019

Relation: 2019 IEEE International Electron Devices Meeting (IEDM)

Linking Room- and Low-Temperature Electrical Performance of MOS Gate Stacks for Cryogenic Applications

Authors: Kao, K.-H., Godfrin, C., Elsayed, A., Li, R., Simoen, E., Grill, A., Kubicek, S., Radu, I. P., Govoreanu, B.

Source: IEEE electron device letters. 43(5):674-677

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCvdc_100148125034.0x000001&indx=1&recIds=ETOCvdc_100148125034.0x000001

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION

Authors: Su, C.-J., Tang, Y.-T, Tsou, Y.-C., Sung, P.-J., Hou, F.-J., Wang, C.-J., Chung, S.-T., Hsieh, C.-Y., Yeh, Y.-S., Hsueh, F.-K., Kao, K.-H., Chuang, S.-S., Wu, C.-T., You, T.-Y., Jian, Y.-L., Chou, T.-H., Shen, Y.-L., Chen, B.-Y., Luo, G.-L., Hong, T.-C., Huang, K.-P., Chen, M.-C., Lee, Y.-J., Chao, T.-S., Tseng, T.-Y., Wu, W.-F., Huang, G.-W., Shieh, J.-M., Yeh, W.-K., Wang, Y.-H.

Source: 2017 Symposium on VLSI Technology VLSI Technology, 2017 Symposium on. :T152-T153 Jun, 2017

Relation: 2017 Symposium on VLSI Technology

Si-based tunnel field-effect transistors for low-power nano-electronics

Authors: Verhulst, A.S., Vandenberghe, W.G., Leonelli, D., Rooyackers, R., Vandooren, A., Zhuge, J., Kao, K-H., Soree, B., Magnus, W., Fischetti, M.V., Pourtois, G., Huyghebaert, C., Huang, R., Wang, Y., De Meyer, K., Dehaene, W., Heyns, M.M., Groeseneken, G.

Source: 69th Device Research Conference Device Research Conference (DRC), 2011 69th Annual. :193-196 Jun, 2011

Relation: 2011 69th Annual Device Research Conference (DRC)

Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

Authors: Sung, P.-J., Chang, C.-Y., Chen, L.-Y., Kao, K.-H., Su, C.-J., Liao, T.-H., Fang, C.-C., Wang, C.-J., Hong, T.-C., Jao, C.-Y., Hsu, H.-S., Luo, S.-X., Wang, Y.-S., Huang, H.-F., Li, J.-H., Huang, Y.-C., Hsueh, F.-K., Wu, C.-T., Huang, Y.-M., Hou, F.-J., Luo, G.-L., Shen, Y.-L., Ma, W. C.-Y., Huang, K.-P., Lin, K.-L., Samukawa, S., Li, Y., Huang, G.-W, Lee, Y.-J., Li, J.-Y., Wu, W.-F., Shieh, J.-M., Chao, T.-S., Yeh, W.-K., Wang, Y.-H.

Source: 2018 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2018 IEEE International. :21.4.1-21.4.4 Dec, 2018

Relation: 2018 IEEE International Electron Devices Meeting (IEDM)

Fabrication and Analysis of a ${\rm Si}/{\rm Si}_{0.55}{\rm Ge}_{0.45}$ Heterojunction Line Tunnel FET

Authors: Walke, A. M., Vandooren, A., Rooyackers, R., Leonelli, D., Hikavyy, A., Loo, R., Verhulst, A. S., Kao, K.-H., Huyghebaert, C., Groeseneken, G., Rao, V. R., Bhuwalka, K. K., Heyns, M. M., Collaert, N., Thean, A. V.-Y.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 61(3):707-715 Mar, 2014

Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field-Effect Transistors

Authors: Verreck, D., Verhulst, A. S., Kao, K.-H., Vandenberghe, W. G., De Meyer, K., Groeseneken, G.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 60(7):2128-2134 Jul, 2013