45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications

Authors: Okuno, M., Okabe, K., Sakuma, T., Suzuki, K., Miyashita, T., Yao, T., Morioka, H., Terahara, M., Kojima, Y., Watatani, H., Sugimoto, K., Watanabe, T., Hayami, Y., Mori, T., Kubo, T., Iba, Y., Sugiura, I., Fukutome, H., Morisaki, Y., Minakata, H., Ikeda, K., Kishii, S., Shimizu, N., Tanaka, T., Asai, S., Nakaishi, M., Fukuyama, S., Tsukune, A., Yamabe, M., Hanyuu, I., Miyajima, M., Kase, M., Watanabe, K., Satoh, S., Sugii, T.

Source: IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. International Electron Devices Meeting 2005 Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International. :52-55 2005

Relation: International Electron Devices Meeting 2005