High speed (1ns) and low voltage (1.5V) demonstration of 8Kb SOT-MRAM array

Authors: Song, M. Y., Lee, C. M., Yang, S. Y., Chen, G. L., Chen, K. M., Wang, I J., Hsin, Y. C., Chang, K. T., Hsu, C. F., Li, S. H., Wei, J. H., Lee, T. Y., Chang, M. F., Bao, X. Y., Diaz, C. H., Lin, S. J.

Source: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2022 IEEE Symposium on. :377-378 Jun, 2022

Relation: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Short-Channel Double-Gate FETs with Atomically Precise Graphene Nanoribbons

Authors: Mutlu, Z., Lin, Y., Barin, G. B., Zhang, Z., Pitner, G., Wang, S., Darawish, R., Giovannantonio, M. Di, Wang, H., Cai, J., Passlack, M., Diaz, C. H., Narita, A., Mullen, K., Fischer, F. R., Bandaru, P., Kummel, A. C., Ruffieux, P., Fasel, R., Bokor, J.

Source: 2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :37.4.1-37.4.4 Dec, 2021

Relation: 2021 IEEE International Electron Devices Meeting (IEDM)

Cold CMOS as a Power-Performance-Reliability Booster for Advanced FinFETs

Authors: Chiang, H. L., Chen, T. C., Wang, J. F., Mukhopadhyay, S., Lee, W. K., Chen, C. L., Khwa, W. S., Pulicherla, B., Liao, P. J., Su, K. W., Yu, K. F., Wang, T., Wong, H. S. P., Diaz, C. H., Cai, J.

Source: 2020 IEEE Symposium on VLSI Technology VLSI Technology, 2020 IEEE Symposium on. :1-2 Jun, 2020

Relation: 2020 IEEE Symposium on VLSI Technology

Electrostatics and ballistic transport studies in junctionless nanowire transistors

Authors: Yu, T.-H., Hsu, Ethan, Liu, C.-W., Colinge, J.-P., Sheu, Y.-M., Wu, Jeff, Diaz, C. H.

Source: 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on. :85-88 Sep, 2013

Relation: 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

Expanding role of predictive TCAD in advanced technology development

Authors: Wu, Jeff, Diaz, C. H.

Source: 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on. :167-171 Sep, 2013

Relation: 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping

Authors: van Dal, M. J. H., Vellianitis, G., Duriez, B., Doornbos, G., Hsieh, C.-H., Lee, B.-H., Yin, K.-M., Passlack, M., Diaz, C. H.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 61(2):430-436 Feb, 2014

Electrical Characteristics of ${\rm Al}_{2}{\rm O}_{3}/{\rm InSb}$ MOSCAPs and the Effect of Postdeposition Annealing Temperatures

Authors: Trinh, H. D., Lin, Y. C., Chang, E. Y., Lee, C.-T., Wang, S.-Y., Nguyen, H. Q., Chiu, Y. S., Luc, Q. H., Chang, H.-C., Lin, C.-H., Jang, S., Diaz, C. H.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 60(5):1555-1560 May, 2013

PCM-Based Analog Compute-In-Memory: Impact of Device Non-Idealities on Inference Accuracy

Authors: Sun, X., Khwa, W. S., Chen, Y. S., Lee, C. H., Lee, H. Y., Yu, S. M., Naous, R., Wu, J. Y., Chen, T. C., Bao, X., Chang, M. F., Diaz, C. H., Wong, H.-S. P., Akarvardar, K.

Source: IEEE transactions on electron devices. 68(11):5585-5591

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCvdc_100132545913.0x000001&indx=1&recIds=ETOCvdc_100132545913.0x000001

Transistor-and Circuit-Design Optimization for Low-Power CMOS

Authors: Chang, M.-C., Chang, C.-S., Chao, C.-P., Goto, K.-I., Ieong, M., Lu, L.-C., Diaz, C. H.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 55(1):84-95 Jan, 2008

Comparative Study of High-$k/{\rm GaSb}$ Interfaces for Use in Antimonide Based MOSFETs

Authors: Bhuwalka, K. K., Wang, S. W., Noriega, O. C., Holland, M. C., Contreras-Guerrero, R., Edirisooriya, M., Doornbos, G., Wang, C.-H., Myers, T. H., Droopad, R., Passlack, M., Diaz, C. H.

Source: IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 35(1):21-23 Jan, 2014

Electrical Characterization and Materials Stability Analysis of ${\rm La}_{2}{\rm O}_{3}/{\rm HfO}_{2}$ Composite Oxides on n-${\rm In}_{0.53}{\rm Ga}_{0.47}{\rm As}$ MOS Capacitors With Different Annealing Temperatures

Authors: Lin, Y. C., Trinh, H. D., Chuang, T. W., Iwai, H., Kakushima, K., Ahmet, P., Lin, C. H., Diaz, C. H., Chang, H. C., Jang, S. M., Chang, E. Y.

Source: IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 34(10):1229-1231 Oct, 2013

An Ultralow-Resistance Ultrashallow Metallic Source/Drain Contact Scheme for III–V NMOS

Authors: Oxland, R., Chang, S. W., Li, X., Wang, S. W., Radhakrishnan, G., Priyantha, W., van Dal, M. J. H., Hsieh, C. H., Vellianitis, G., Doornbos, G., Bhuwalka, K., Duriez, B., Thayne, I., Droopad, R., Passlack, M., Diaz, C. H., Sun, Y. C.

Source: IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 33(4):501-503 Apr, 2012

Integrated Stress and Process Calibration in Strained-Si Devices

Authors: Yu, T.-H., Tu, K.-C., Sheu, Y.-M., Diaz, C. H.

Source: 2009 International Conference on Simulation of Semiconductor Processes and Devices Simulation of Semiconductor Processes and Devices, 2009. SISPAD '09. International Conference on. :1-4 Sep, 2009

Relation: 2009 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

32nm gate-first high-k/metal-gate technology for high performance low power applications

Authors: Diaz, C. H., Goto, K., Huang, H.T., Yasuda, Yuri, Tsao, C.P., Chu, T.T., Lu, W.T., Chang, Vincent, Hou, Y.T., Chao, Y.S., Hsu, P.F., Chen, C.L., Lin, K.C., Ng, J.A., Yang, W.C., Chen, C.H., Peng, Y.H., Chen, C.J., Chen, C.C., Yu, M..H., Yeh, L.Y., You, K.S., Chen, K.S., Thei, K.B., Lee, C.H., Yang, S.H., Cheng, J.Y., Huang, K.T., Liaw, J.J., Ku, Y., Jang, S.M., Chuang, H., Liang, M.S.

Source: 2008 IEEE International Electron Devices Meeting Electron Devices Meeting, 2008. IEDM 2008. IEEE International. :1-4 Dec, 2008

Relation: 2008 IEEE International Electron Devices Meeting (IEDM)

A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm2 SRAM cell

Authors: Cheng, Kuan-Lun, Wu, C. C., Wang, Y. P., Lin, D. W., Chu, C. M., Tarng, Y. Y., Lu, S. Y., Yang, S. J., Hsieh, M. H., Liu, C. M., Fu, S. P., Chen, J. H., Lin, C. T., Lien, W. Y., Huang, H. Y., Wang, P. W., Lin, H. H., Lee, D. Y., Huang, M. J., Nieh, C. F., Lin, L. T., Chen, C. C., Chang, W., Chiu, Y. H., Wang, M. Y., Yeh, C. H., Chen, F. C., Wu, C. M., Chang, Y. H., Wang, S. C., Hsieh, H. C., Lei, M. D., Goto, K., Tao, H. J., Cao, M., Tuan, H. C., Diaz, C. H., Mii, Y. J.

Source: 2007 IEEE International Electron Devices Meeting Electron Devices Meeting, 2007. IEDM 2007. IEEE International. :243-246 Dec, 2007

Relation: 2007 IEEE International Electron Devices Meeting

A Millisecond-Anneal-Assisted Selective Fully Silicided (FUSI) Gate Process

Authors: Lin, D.-W., Wang, M., Cheng, M.-L., Sheu, Y.-M., Tarng, B., Chu, C.-M., Nieh, C.-W., Lo, C.-P., Tsai, W.-C., Lin, R., Wang, S.-W., Cheng, K.-L., Wu, C.-M., Lei, M.-T., Wu, C.-C., Diaz, C. H., Chen, M.-J.

Source: IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 29(9):998-1000 Sep, 2008

InAs N-MOSFETs with record performance of Ion = 600 μA/μm at Ioff = 100 nA/μm (Vd = 0.5 V)

Authors: Chang, S. W., Li, Xu, Oxland, R., Wang, S. W., Wang, C. H., Contreras-Guerrero, R., Bhuwalka, K. K., Doornbos, G., Vasen, T., Holland, M. C., Vellianitis, G., van Dal, M. J. H., Duriez, B., Edirisooriya, M., Rojas-Ramirez, J. S, Ramvall, P., Thoms, S., Peralagu, U., Hsieh, C. H., Chang, Y. S., Yin, K. M., Lind, E., Wernersson, L.-E., Droopad, R., Thayne, I., Passlack, M., Diaz, C. H.

Source: 2013 IEEE International Electron Devices Meeting Electron Devices Meeting (IEDM), 2013 IEEE International. :16.1.1-16.1.4 Dec, 2013

Relation: 2013 IEEE International Electron Devices Meeting (IEDM)

Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafers

Authors: Duriez, B., Vellianitis, G., van Dal, M. J. H., Doornbos, G., Oxland, R., Bhuwalka, K. K., Holland, M., Chang, Y. S., Hsieh, C. H., Yin, K. M., See, Y. C., Passlack, M., Diaz, C. H.

Source: 2013 IEEE International Electron Devices Meeting Electron Devices Meeting (IEDM), 2013 IEEE International. :20.1.1-20.1.4 Dec, 2013

Relation: 2013 IEEE International Electron Devices Meeting (IEDM)

Demonstration of scaled Ge p-channel FinFETs integrated on Si

Authors: van Dal, M.J.H., Vellianitis, G., Doornbos, G., Duriez, B., Shen, T. M, Wu, C. C., Oxland, R., Bhuwalka, K., Holland, M., Lee, T. L., Wann, C., Hsieh, C. H., Lee, B. H., Yin, K. M., Wu, Z. Q., Passlack, M., Diaz, C. H.

Source: 2012 International Electron Devices Meeting Electron Devices Meeting (IEDM), 2012 IEEE International. :23.5.1-23.5.4 Dec, 2012

Relation: 2012 IEEE International Electron Devices Meeting (IEDM)

Mobility Enhancement and Strain Integration in Advanced CMOS
Silicon materials science and technology

Authors: Diaz, C. H.

Source: ECS TRANSACTIONS. 2(2):341-348

Availability: http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCCN065534549&indx=1&recIds=ETOCCN065534549