Observation of room temperature gate tunable quantum confinement effect in photodoped junctionless MOSFET

Authors: Khan, Biswajit, Mukherjee, Abir, Georgiev, Yordan M., Colinge, J. P., Ghosh, Suprovat, Das, Samaresh

Subject Terms: Condensed Matter - Mesoscale and Nanoscale Physics

Access URL: http://arxiv.org/abs/2403.07324

Back-bias impact on variability and BTI for 3D-monolithic 14nm FDSOI SRAMs applications

Authors: Bosch, D., Andrieu, F., Garros, X., Ciampolini, L., Makosiej, A., Weber, O., Lacord, J., Cluzel, J., Giraud, B., Cibrario, G., Brunet, L., Batude, P., Fenouillet-Beranger, C., Lattard, D., Colinge, J. P., Balestra, F., Vinet, M.

Source: 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Ultimate Integration on Silicon (EUROSOI-ULIS), 2019 Joint International EUROSOI Workshop and International Conference on. :1-4 Apr, 2019

Relation: 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

Laser Processing For 3D Junctionless Transistor Fabrication

Authors: Bosch, D., Alba, P. Acosta, Kerdiles, S., Benevent, V., Perrot, C., Lassarre, J., Richy, J., Lacord, J., Sklenard, B., Brunet, L., Batude, P., Fenouillet-Beranger, C., Lattard, D., Colinge, J. P., Balestra, F., Andrieu, F.

Source: 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019 IEEE. :1-3 Oct, 2019

Relation: 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

Laser Processing For 3D Junctionless Transistor Fabrication

Authors: Bosch, D., Alba, P. Acosta, Kerdiles, S., Benevent, V., Perrot, C., Lassarre, J., Richy, J., Lacord, J., Sklenard, B., Brunet, L., Batude, P., Fenouillet-Beranger, C., Lattard, D., Colinge, J. P., Balestra, F., Andrieu, F.

Subject Terms: Physics - Applied Physics

Access URL: http://arxiv.org/abs/2011.15061

Low temperature high voltage analog devices in a 3D sequential integration

Authors: Cavalcante, C., Garros, X., Batude, P., Tataridou, A., Lacord, J., Casse, M., Theodorou, C., Karatsori, T., Gassilloud, R., Fenouillet-Beranger, C., Brunet, L., Rozeau, O., Rambal, N., Gaillard, F., Ponthenier, F., Allain, F., Romano, G., Ghibaudo, G., Colinge, J-P., Vinet, M., Andrieu, F.

Source: 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) VLSI Technology, Systems and Applications (VLSI-TSA), 2020 International Symposium on. :155-156 Aug, 2020

Relation: 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

All-Operation-Regime Characterization and Modeling of Drain Current Variability in Junctionless and Inversion-Mode FDSOI Transistors

Authors: Bosch, D., Colinge, J. P., Ghibaudo, G., Garros, X., Barraud, S., Lacord, J., Sklenard, B., Brunet, L., Batude, P., Fenouillet-Beranger, C., Cluzel, J., Kies, R., Hartmann, J. M., Vizioz, C., Audoit, G., Balestra, F., Andrieu, F.

Source: 2020 IEEE Symposium on VLSI Technology VLSI Technology, 2020 IEEE Symposium on. :1-2 Jun, 2020

Relation: 2020 IEEE Symposium on VLSI Technology

28nm FDSOI CMOS Technology (FEOL and BEOL) Thermal Stability for 3D Sequential Integration: Yield and Reliability Analysis

Authors: Cavalcante, C., Fenouillet-Beranger, C., Batude, P., Garros, X., Federspiel, X., Lacord, J., Kerdiles, S., Royet, A. S., Acosta-Alba, P., Rozeau, O., Barral, V., Arnaud, F., Planes, N., Sassoulas, P. O., Ghegin, E., Beneyton, R., Gregoire, M., Weber, O., Guerin, C., Arnaud, L., Moreau, S., Kies, R., Romano, G., Rambal, N., Magalhaes, A., Ghibaudo, G., Colinge, J. P., Vinet, M., Andrieu, F.

Source: 2020 IEEE Symposium on VLSI Technology VLSI Technology, 2020 IEEE Symposium on. :1-2 Jun, 2020

Relation: 2020 IEEE Symposium on VLSI Technology

Impact of Low-Temperature Coolcube™ Process on the Performance of FDSOI Tunnel FETs

Authors: Diaz-Llorente, C., Colinge, J.-P., Le Royer, C., Vinet, M., Theodorou, C. G., Cristoloveanu, S., Ghibaudo, G.

Source: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018 IEEE. :1-3 Oct, 2018

Relation: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

Novel Fine-Grain Back-Bias Assist Techniques for 14nm FDSOI Top-Tier SRAMs integrated in 3D-Monolithic

Authors: Bosch, D., Andrieu, F., Ciampolini, L., Makosiej, A., Weber, O., Garros, X., Lacord, J., Cluzel, J., Esmanhotto, E., Rios, M., Lang, S., Giraud, B., Berthelon, R., Cibrario, G., Brunet, L., Batude, P., Fenouillet-Beranger, C., Lattard, D., Colinge, J. P., Balestra, F., Vinet, M.

Source: 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) VLSI Technology, Systems and Application (VLSI-TSA), 2019 International Symposium on. :1-2 Apr, 2019

Relation: 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

Multigate transistors: Pushing Moore's law to the limit

Authors: Colinge, J.-P.

Source: 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) Simulation of Semiconductor Processes and Devices (SISPAD), 2014 International Conference on. :313-316 Sep, 2014

Relation: 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

Electrostatics and ballistic transport studies in junctionless nanowire transistors

Authors: Yu, T.-H., Hsu, Ethan, Liu, C.-W., Colinge, J.-P., Sheu, Y.-M., Wu, Jeff, Diaz, C. H.

Source: 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on. :85-88 Sep, 2013

Relation: 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

Towards 500°C SPER activated devices for 3D sequential integration

Authors: Micout, J., Sklenard, B., Batude, P., Berthelon, R., Rafhay, Q., Lacord, J., Mathieu, B., Pasini, L., Saghi, Z., Delaye, V., Brunet, L., Fenouillet-Beranger, C., Joblot, S., Mazen, F., Mazzocchi, V., Colinge, J-P., Ghibaudo, G., Vinet, M.

Source: 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017 IEEE. :1-2 Oct, 2017

Relation: 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

Novel gate concepts for MOS devices

Authors: Colinge, J.-P.

Source: Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Solid-state device research conference Solid-State Device Research Conference, 2004. ESSDERC 2004. Proceeding of the 34th European. :45-49 2004

Relation: Proceedings of the 34th European Solid-State Device Research Conference

3D Sequential Integration: Application-driven technological achievements and guidelines

Authors: Batude, P., Brunet, L., Fenouillet-Beranger, C., Andrieu, F., Colinge, J.-P., Lattard, D., Vianello, E., Thuries, S., Billoint, O., Vivet, P., Santos, C., Mathieu, B., Sklenard, B., Lu, C.-M. V., Micout, J., Deprat, F., Mercado, E. Avelar, Ponthenier, F., Rambal, N., Samson, M.-P., Casse, M., Hentz, S., Arcamone, J., Sicard, G., Hutin, L., Pasini, L., Ayres, A., Rozeau, O., Berthelon, R., Nemouchi, F., Rodriguez, P., Pin, J.-B., Larmagnac, D., Duboust, A., Ripoche, V., Barraud, S., Allouti, N., Barnola, S., Vizioz, C., Hartmann, J.-M., Kerdiles, S., Alba, P. Acosta, Beaurepaire, S., Beugin, V., Fournel, F., Besson, P., Loup, V., Gassilloud, R., Martin, F., Garros, X., Mazen, F., Previtali, B., Euvrard-Colnat, C., Balan, V., Comboroure, C., Zussy, M., Mazzocchi, Faynot, O., Vinet, M.

Source: 2017 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2017 IEEE International. :3.1.1-3.1.4 Dec, 2017

Relation: 2017 IEEE International Electron Devices Meeting (IEDM)

High performance low temperature FinFET with DSPER, gate last and Self Aligned Contact for 3D sequential mtegration

Authors: Micout, J., Lapras, V., Batude, P., Fenouillet-Beranger, C., Lacord, J., Sklenard, B., Mathieu, B., Rafhay, Q., Mazzocchi, V., Colinge, J.-P., Lachal, L., Garros, X., Casse, M., Toffoli, A., Romano, G., Allain, F., Brunet, L., Hartmann, J.-M., Bortolin, R., Mazen, F., Barraud, S., Rambal, N., Tabone, C., Samson, M.-P., Besombes, P., Delaye, V., Saghi, Z., Loup, V., Comboroure, C., Balan, V., Desvoivres, L., Vizioz, C., Ghibaudo, G., Vinet, M.

Source: 2017 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2017 IEEE International. :32.2.1-32.2.4 Dec, 2017

Relation: 2017 IEEE International Electron Devices Meeting (IEDM)

Extraction of channel mobility in nanowire MOSFETs using Id(Vg) characteristics and random telegraph noise amplitude

Authors: Nazarov, A. N., Lee, C. W., Kranti, A., Ferain, I., Yan, R., Akhavan, N. Dehdashti, Razavi, P., Yu, R., Colinge, J.-P.

Source: Ulis 2011 Ultimate Integration on Silicon Ultimate Integration on Silicon (ULIS), 2011 12th International Conference on. :1-3 Mar, 2011

Relation: 2011 12th International Conference on Ultimate Integration on Silicon (ULIS)

Performance investigation of short-channel junctionless multigate transistors

Authors: Razavi, P., Fagas, G., Ferain, I., Akhavan, N. Dehdashti, Yu, R., Colinge, J. P.

Source: Ulis 2011 Ultimate Integration on Silicon Ultimate Integration on Silicon (ULIS), 2011 12th International Conference on. :1-3 Mar, 2011

Relation: 2011 12th International Conference on Ultimate Integration on Silicon (ULIS)

Device Design and Estimated Performance for p-Type Junctionless Transistors on Bulk Germanium Substrates

Authors: Yu, R., Das, S., Ferain, I., Razavi, P., Shayesteh, M., Kranti, A., Duffy, R., Colinge, J.-P.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 59(9):2308-2313 Sep, 2012

SOI devices and circuits

Authors: Colinge, J.-P.

Source: 2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Microelectronics Microelectronics, 2000. Proceedings. 2000 22nd International Conference on. 2:407-414 vol.2 2000

Relation: 2000 22nd International Conference on Microelectronics. Proceedings

Junctionless Multiple-Gate Transistors for Analog Applications

Authors: Doria, R. T., Pavanello, M. A., Trevisoli, R. D., de Souza, M., Lee, C.-W., Ferain, I., Akhavan, N. D., Yan, R., Razavi, P., Yu, R., Kranti, A., Colinge, J.-P.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 58(8):2511-2519 Aug, 2011