Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model

Authors: Yu-Ju Shih, Chih-Tsun Huang, Jing-Jia Liou, Jyu-Yuan Lai, Chih-Wea Wang, Chi-Feng Wu

Source: 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) VLSI Design, Automation and Test (VLSI-DAT), 2017 International Symposium on. :1-4 Apr, 2017

Relation: 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

Test for more than pass/fail using on-chip temperature sensor

Authors: Chih-Wea Wang, Lin, Chen-Tung, Chun-Chieh Hsu, Ching-Tung Wu, Chi-Feng Wu

Source: Proceedings of Technical Program of 2012 VLSI Design, Automation and Test VLSI Design, Automation, and Test (VLSI-DAT), 2012 International Symposium on. :1-4 Apr, 2012

Relation: 2012 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

A configurable SystemC virtual platform for early software development and its sub-system for hardware verification

Authors: Yong-Hua Bu, Zhen-Zhong Tao, Ming-Ju Lei, Ching-Tung Wu, Chi-Feng Wu

Source: Proceedings of 2010 International Symposium on VLSI Design, Automation and Test VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on. :29-32 Apr, 2010

Relation: 2010 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

Flash memory built-in self-test using March-like algorithms

Authors: Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu

Source: Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002 Electronic design, test and applications Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on. :137-141 2002

Relation: Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002

A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters

Authors: Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang

Source: Proceedings 10th Asian Test Symposium Asian test symposium Test Symposium, 2001. Proceedings. 10th Asian. :103-108 2001

Relation: Tenth Asian Test Symposium

Simulation-based test algorithm generation and port scheduling for multi-port memories

Authors: Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu

Source: Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) Design automation conference Design Automation Conference, 2001. Proceedings. :301-306 2001

Relation: Proceedings 2001. 38th Design Automation Conference

Error catch and analysis for semiconductor memories using March tests

Authors: Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu

Source: IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140) Computer aided design ICCAD 2000 Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on. :468-471 2000

Relation: Proceedings of International Conference on Computer Aided Design (ICCAD)

Simulation-based test algorithm generation for random access memories

Authors: Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu

Source: Proceedings 18th IEEE VLSI Test Symposium VLSI test symposium VLSI Test Symposium, 2000. Proceedings. 18th IEEE. :291-296 2000

Relation: Proceedings 18th IEEE VLSI Test Symposium

A built-in self-test and self-diagnosis scheme for embedded SRAM

Authors: Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Teng, T., Chiu, K., Hsiao-Ping Lin

Source: Proceedings of the Ninth Asian Test Symposium Asian test symposium Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian. :45-50 2000

Relation: Proceedings of the Ninth Asian Test Symposium

Fault detection and location of dynamic reconfigurable FPGAs

Authors: Chi-Feng Wu, Cheng-Wen Wu

Source: 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453) VLSI technology, systems, and applications VLSI Technology, Systems, and Applications, 1999. International Symposium on. :215-218 1999

Relation: Proceedings of International Symposium on VLSI Technology Systems and Applications

Testing interconnects of dynamic reconfigurable FPGAs

Authors: Chi-Feng Wu, Cheng-Wen Wu

Source: Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Design automation Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific. :279-282 vol.1 1999

Relation: Proceedings of the ASP-DAC '99 Asian and South Pacific Design Automation Conference 1999

RAMSES: a fast memory fault simulator

Authors: Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu

Source: Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Defect and fault tolerance in VLSI systems Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on. :165-173 1999

Relation: 1999 Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Design of single-ended SRAM with high test coverage and short test time

Authors: Chi-Feng Wu, Chua-Chin Wang, Rain-Ted Hwang, Chia-Hsiung Kao

Source: 1998 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and systems Circuits and Systems (ISCAS), 1998 IEEE International Symposium on. 2:292-295 vol.2 1998

Relation: 1998 IEEE International Symposium on Circuits and Systems (ISCAS)

Built-in redundancy analysis for memory yield improvement

Authors: Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu

Source: IEEE Transactions on Reliability IEEE Trans. Rel. Reliability, IEEE Transactions on. 52(4):386-399 Dec, 2003

High fan-in dynamic CMOS comparators with low transistor count

Authors: Chua-Chin Wang, Po-Ming Lee, Chi-Feng Wu, Hsin-Long Wu

Source: IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications IEEE Trans. Circuits Syst. I Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on. 50(9):1216-1220 Sep, 2003

Fault simulation and test algorithm generation for random access memories

Authors: Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 21(4):480-490 Apr, 2002

Image processing techniques for wafer defect cluster identification

Authors: Chenn-Jung Huang, Chi-Feng Wu, Chua-Chin Wang

Source: IEEE Design & Test of Computers IEEE Des. Test. Comput. Design & Test of Computers, IEEE. 19(2):44-48 Apr, 2002

On-chip interconnection design and SoC integration with OCP

Authors: Chih-Wea Wang, Chi-Shao Lai, Chi-Feng Wu, Shih-Arn Hwang, Ying-Hsi Lin

Source: 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on. :25-28 Apr, 2008

Relation: 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

Single-ended SRAM with high test coverage and short test time

Authors: Chua-Chin Wang, Chi-Feng Wu, Rain-Ted Hwang, Chia-Hsiung Kao

Source: IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 35(1):114-118 Jan, 2000

A low-power and high-speed dynamic PLA circuit configuration for single-clock CMOS

Authors: Chua-Chin Wang, Chi-Feng Wu, Rain-Ted Hwang, Chia-Hsiung Kao

Source: IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications IEEE Trans. Circuits Syst. I Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on. 46(7):857-861 Jul, 1999