Cell-Aware Test on Various Circuits in an Advanced 3-nm Technology

Authors: Gao, Z., Hu, M., Baert, R., Chehab, B., Swenton, J., Malagi, S., Huisken, J., Goossens, K., Marinissen, E.J.

Source: IEEE Design & Test IEEE Des. Test Design & Test, IEEE. 41(2):56-64 Apr, 2024

Increasing Functionality of Wafer’s Backside: Analysis of Si and WS₂ Backside Power-Switch

Authors: Mirabelli, G., Chen, R., Ahmed, Z., Chehab, B., Zografos, O., Hiblot, G., Weckx, P., Hellings, G., Ryckaert, J.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 70(7):3970-3974 Jul, 2023

Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era

Authors: Sisto, G., Zografos, O., Chehab, B., Kakarla, N., Xiang, Y., Milojevic, D., Weckx, P., Hellings, G., Ryckaert, J.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 30(10):1497-1506 Oct, 2022

The Complementary FET (CFET) 6T-SRAM

Authors: Gupta, M.K., Weckx, P., Schuddinck, P., Jang, D., Chehab, B., Cosemans, S., Ryckaert, J., Dehaene, W.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 68(12):6106-6111 Dec, 2021

Process Integration of High Aspect Ratio Vias with a Comparison between Co and Ru Metallizations

Authors: Vega-Gonzalez, V., Montero, D., Versluijs, J., Pedreira, O. Varela, Jourdan, N., Puliyalil, H., Chehab, B., Peissker, T., Haider, A., Batuk, D., Martinez, G. T., Geypen, J., Le, Q. T., Bazzazian, N., Heylen, N., van der Veen, M., El-Mekki, Z., Webers, T., Vats, H., Rynders, L., Cupak, M., Uk-Lee, J., Drissi, Y., Halipre, L., Gillijns, W., Charley, A.-L., Verdonck, P., Witters, T., Gompel, S. V., Kimura, Y., Ciofi, I., De Wachter, B., Swerts, J., Grieten, E., Ercken, M., Kim, R., Croes, K., Leray, P., Jaysankar, M., Nagesh, N., Ramakers, L., Murdoch, G., Park, S., Tokei, Z., Dentoni-Litta, E., Horiguchi, N.

Source: 2021 IEEE International Interconnect Technology Conference (IITC) Interconnect Technology Conference (IITC), 2021 IEEE International. :1-3 Jul, 2021

Relation: 2021 IEEE International Interconnect Technology Conference (IITC)

IR-Drop Analysis of Hybrid Bonded 3D-ICs with Backside Power Delivery and μ- & n- TSVs

Authors: Sisto, G., Chehab, B., Genneret, B., Baert, R., Chen, R., Weckx, P., Ryckaert, J., Chou, R., van Der Plas, G., Beyne, E., Milojevic, D.

Source: 2021 IEEE International Interconnect Technology Conference (IITC) Interconnect Technology Conference (IITC), 2021 IEEE International. :1-3 Jul, 2021

Relation: 2021 IEEE International Interconnect Technology Conference (IITC)

A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node

Authors: Gupta, M.K., Weckx, P., Schuddinck, P., Jang, D., Chehab, B., Cosemans, S., Ryckaert, J., Dehaene, W.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 68(8):3819-3825 Aug, 2021

Disruptive Technology Elements, and Rapid and Accurate Block-Level Performance Evaluation for 3nm and Beyond

Authors: Na, M.H., Jang, D., Baert, R., Sarkar, S., Patli, S., Zografos, O., Chehab, B., Spessot, A., Sisto, G., Schuddinck, P., Mertens, H., Oniki, Y., Hellings, G., Litta, E. Dentoni, Ryckaert, J., Horiguchi, N.

Source: 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) Electron Devices Technology & Manufacturing Conference (EDTM), 2021 5th IEEE. :1-3 Apr, 2021

Relation: 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)

PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch

Authors: Schuddinck, P., Bufler, F. M., Xiang, Y., Farokhnejad, A., Mirabelli, G., Vandooren, A., Chehab, B., Gupta, A., Neve, C. Roda, Hellings, G., Ryckaert, J.

Source: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2022 IEEE Symposium on. :365-366 Jun, 2022

Relation: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Authors: Gupta, A., Pedreira, O.V., Arutchelvan, G., Zahedmanesh, H., Devriendt, K., Mertens, H., Tao, Z., Ritzenthaler, R., Wang, S., Radisic, D., Kenis, K., Teugels, L., Sebai, F., Lorant, C., Jourdan, N., Chan, B.T., Subramanian, S., Schleicher, F., Hopf, T., Peter, A.P., Rassoul, N., Debruyn, H., Demonie, I., Siew, Y.K., Chiarella, T., Briggs, B., Zhou, X., Rosseel, E., De Keersgieter, A., Capogreco, E., Litta, E.D., Boccardi, G., Baudot, S., Mannaert, G., Bontemps, N., Sepulveda, A., Mertens, S., Kim, M., Dupuy, E., Vandersmissen, K., Paolillo, S., Yakimets, D., Chehab, B., Favia, P., Drijbooms, C., Cousserier, J., Jaysankar, M., Lazzarino, F., Morin, P., Altamirano, E., Mitard, J., Wilson, C.J., Holsteyns, F., Boemmels, J., Demuynck, S., Tokei, Z., Horiguchi, N.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 67(12):5349-5354 Dec, 2020

Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space

Authors: Mertens, H., Ritzenthaler, R., Oniki, Y., Briggs, B., Chan, B.T., Hikavyy, A., Hopf, T., Mannaert, G., Tao, Z., Sebaai, F., Peter, A., Vandersmissen, K., Dupuy, E., Rosseel, E., Batuk, D., Geypen, J., Martinez, G. T., Abigail, D., Grieten, E., Dehave, K., Mitard, J., Subramanian, S., Ragnarsson, L.-A., Weckx, P., Jang, D., Chehab, B., Hellings, G., Ryckaert, J., Litta, E. Dentoni, Horiguchi, N.

Source: 2021 Symposium on VLSI Technology VLSI Technology, 2021 Symposium on. :1-2 Jun, 2021

Relation: 2021 Symposium on VLSI Technology

From Design to System-Technology optimization for CMOS

Authors: Ryckaert, J., Chehab, B., Jang, D., Mirabelli, G., Salahuddin, S.M., Schuddinck, P., Zografos, O., Zubair, A., Weckx, Pieter, Hellings, Geert

Source: 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) VLSI Technology, Systems and Applications (VLSI-TSA), 2021 International Symposium on. :1-2 Apr, 2021

Relation: 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

Authors: Chen, R., Sisto, G., Jourdain, A., Hiblot, G., Stucchi, M., Kakarla, N., Chehab, B., Salahuddin, S. M., Schleicher, F., Veloso, A., Hellings, G., Weckx, P., Milojevic, D., Van der Plas, G., Ryckaert, J., Beyne, E.

Source: 2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :22.4.1-22.4.4 Dec, 2021

Relation: 2021 IEEE International Electron Devices Meeting (IEDM)

Extended Scale Length Theory Targeting Low-Dimensional FETs for Carbon Nanotube FET Digital Logic Design-Technology Co-optimization

Authors: Gilardi, C., Chehab, B., Sisto, G., Schuddinck, P., Ahmed, Z., Zografos, O., Lin, Q., Hellings, G., Ryckaert, J., Wong, H.-S.P., Mitra, S.

Source: 2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :27.3.1-27.3.4 Dec, 2021

Relation: 2021 IEEE International Electron Devices Meeting (IEDM)

Buried Power Rail Metal exploration towards the 1 nm Node

Authors: Gupta, A., Radisic, D., Maes, J. W., Pedreira, O. Varela, Soulie, J-P., Jourdan, N., Mertens, H., Bandyopadhyay, S., Le, Q. T., Pacco, A., Heylen, N., Vandersmissen, K., Devriendt, K., Zhu, C., Datta, S., Sebaai, F., Wang, S., Mousa, M., Lee, J., Geypen, J., De Wachter, B., Chehab, B., Salahuddin, S. M., Murdoch, G., Biesemans, S., Tokei, Zs., Litta, E. Dentoni, Horiguchi, N.

Source: 2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :22.5.1-22.5.4 Dec, 2021

Relation: 2021 IEEE International Electron Devices Meeting (IEDM)

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

Authors: Gupta, A., Mertens, H., Tao, Z., Demuynck, S., Bommels, J., Arutchelvan, G., Devriendt, K., Pedreira, O. Varela, Ritzenthaler, R., Wang, S., Radisic, D., Kenis, K., Teugels, L., Sebaai, F., Lorant, C., Jourdan, N., Chan, B. T., Zahedmanesh, H., Subramanian, S., Schleicher, F., Hopf, T., Peter, A., Rassoul, N., Debruyn, H., Demonie, I., Siew, Y., Chiarella, T., Briggs, B., Zhou, D., Rosseel, E., De Keersgieter, A., Capogreco, E., Litta, E. Dentoni, Boccardi, G., Baudot, S., Mannaert, G., Bontemps, N., Sepulveda, A., Mertens, S., Kim, M. S., Dupuy, E., Vandersmissen, K., Paolillo, S., Yakimets, D., Chehab, B., Favia, P., Drijbooms, C., Cousserier, J., Jaysankar, M., Lazzarino, F., Morin, P., Sanchez, E., Mitard, J., Wilson, C., Holsteyns, F., Tokei, Z., Horiguchi, N.

Source: 2020 IEEE Symposium on VLSI Technology VLSI Technology, 2020 IEEE Symposium on. :1-2 Jun, 2020

Relation: 2020 IEEE Symposium on VLSI Technology

Effect of inter layer cold work on 2024 aluminium alloy produced by wire directed energy deposition

Authors: Eimer, E., Ganguly, S., Czink, S., Dietrich, S., Chehab, B., Ding, J., Williams, S.

Source: In Materials Science & Engineering A 26 July 2023 880

Introducing 2D-FETs in Device Scaling Roadmap using DTCO

Authors: Ahmed, Z., Afzalian, A., Schram, T., Jang, D., Verreck, D., Smets, Q., Schuddinck, P., Chehab, B., Sutar, S., Arutchelvan, G., Soussou, A., Asselberghs, I., Spessot, A., Radu, I. P., Parvais, B., Ryckaert, J., Na, M. H.

Source: 2020 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2020 IEEE International. :22.5.1-22.5.4 Dec, 2020

Relation: 2020 IEEE International Electron Devices Meeting (IEDM)

Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

Authors: Gupta, A., Pedreira, O. Varela, Tao, Z., Mertens, H., Radisic, D., Jourdan, N., Devriendt, K., Heylen, N., Wang, S., Chehab, B., Jang, D., Hellings, G., Sebaai, F., Lorant, C., Teugels, L., Peter, A., Chan, BT, Schleicher, F., Demonie, I., Marien, P., Sepulveda, A., Richard, O., Nagesh, N., Lesniewska, A., Lazzarino, F., Ryckaert, J., Morin, P., Altamirano-Sanchez, E., Murdoch, G., Bommels, J., Demuynck, S., Na, M. H, Tokei, Z., Biesemans, S., Litta, E. Dentoni, Horiguchi, N.

Source: 2020 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2020 IEEE International. :20.3.1-20.3.4 Dec, 2020

Relation: 2020 IEEE International Electron Devices Meeting (IEDM)

Mechanical performances of the interface between the substrate and deposited material in aluminium wire Direct Energy Deposition

Authors: Eimer, E., Williams, S., Ding, J., Ganguly, S., Chehab, B.

Source: In Materials & Design January 2023 225