High RA Dual-MTJ SOT-MRAM devices for High Speed (10ns) Compute-in-Memory Applications

Authors: Song, M. Y., Chen, K. L., Chen, K. M., Chang, K. T., Wang, I. J., Hsin, Y. C., Lin, C. Y., Ambrosi, E., Khwa, Win-San, Lu, Y. L., Hu, C. Y., Yang, S. Y., Li, S. H., Wei, J. H., Lee, T. Y., Wang, Y. J., Chang, M. F., Pai, C. F., Bao, X. Y.

Source: 2023 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2023 International. :1-4 Dec, 2023

Relation: 2023 International Electron Devices Meeting (IEDM)

How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology

Authors: Chiang, H.-L., Hadi, R. A., Wang, J.-F., Han, H.-C., Wu, J.-J., Hsieh, H.-H., Horng, J.-J., Chou, W.-S., Lien, B.-S., Chang, C.-H., Chen, Y.-C., Wang, Y.-H., Chen, T.-C., Liu, J.-C., Liu, Y.-C., Chiang, M.-H., Kao, K.-H., Pulicherla, B., Cai, J., Chang, C.-S., Su, K.-W., Cheng, K.-L., Yeh, T.-J., Peng, Y.-C., Enz, C., Chang, M.-C. F., Chang, M.-F., Wong, H.-S. P., Radu, I. P.

Source: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2023 IEEE Symposium on. :1-2 Jun, 2023

Relation: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

High speed (1ns) and low voltage (1.5V) demonstration of 8Kb SOT-MRAM array

Authors: Song, M. Y., Lee, C. M., Yang, S. Y., Chen, G. L., Chen, K. M., Wang, I J., Hsin, Y. C., Chang, K. T., Hsu, C. F., Li, S. H., Wei, J. H., Lee, T. Y., Chang, M. F., Bao, X. Y., Diaz, C. H., Lin, S. J.

Source: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2022 IEEE Symposium on. :377-378 Jun, 2022

Relation: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Interfacial-Layer Design for Hf1-xZrxO2-Based FTJ Devices: From Atom to Array

Authors: Chiang, H. -L., Wang, J.-F., Lin, K. -H., Nien, C.-H., Wu, J. -J., Hsiang, K.-Y., Chuu, C. -P., Chen, Y.-W., Zhang, X. W., Liu, C. W., Wang, Tahui, Wang, C. -C., Lee, M.-H., Chang, M. -F., Chang, C.-S., Chen, T. C.

Source: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2022 IEEE Symposium on. :361-362 Jun, 2022

Relation: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Engineering defects in pristine amorphous chalcogenides for forming-free low voltage selectors

Authors: Ambrosi, E., Wu, C. H., Lee, H. Y., Hsu, C. F., Lee, C. M., Vaziri, S., Datye, I. M., Chen, Y. Y., Hou, D. H., Chang, P. C., Heh, D. W., Liao, P. J., Lee, T. Y., Chang, M. F., Wong, H.-S. P., Bao, X. Y.

Source: 2022 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2022 International. :18.7.1-18.7.4 Dec, 2022

Relation: 2022 IEEE International Electron Devices Meeting (IEDM)

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

Authors: Si, X., Tu, Y.-N., Huang, W.-H., Su, J.-W., Lu, P.-J., Wang, J.-H., Liu, T.-W., Wu, S.-Y., Liu, R., Chou, Y.-C., Zhang, Z., Sie, S.-H., Wei, W.-C., Lo, Y.-C., Wen, T.-H., Hsu, T.-H., Chen, Y.-K., Shih, W., Lo, C.-C., Liu, R.-S., Hsieh, C.-C., Tang, K.-T., Lien, N.-C., Shih, W.-C., He, Y., Li, Q., Chang, M.-F.

Source: 2020 IEEE International Solid-State Circuits Conference - (ISSCC) Solid-State Circuits Conference - (ISSCC), 2020 IEEE International. :246-248 Feb, 2020

Relation: 2020 IEEE International Solid-State Circuits Conference - (ISSCC)

A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array

Authors: Li, P.-Y., Yang, C.-H., Chen, W.-H., Huang, J.-H., Wei, W.-C., Liu, J.-S., Lin, W.-Y., Hsu, T.H., Hsieh, C.-C., Liu, R.-S., Chang, M.-F., Tang, K.-T.

Source: 2018 IEEE Biomedical Circuits and Systems Conference (BioCAS) Biomedical Circuits and Systems Conference (BioCAS), 2018 IEEE. :1-4 Oct, 2018

Relation: 2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)

Deep insights into Interface Effects to achieve Low-voltage Operation (

Authors: Tang, Y.-T., Wu, T.-M., Fan, C.-L., Lai, Y.-M., Hsiang, K.-Y., Liao, C.-Y., Chang, S.-H., Yu, T.-Y., Su, P., Chang, M.-T., Huang, B.-H., Hu, C., Chang, S.-J., Chang, M.-F., Lee, M.-H.

Source: 2021 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) Radio-Frequency Integration Technology (RFIT), 2021 IEEE International Symposium on. :1-2 Aug, 2021

Relation: 2021 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

MLC PCM Techniques to Improve Nerual Network Inference Retention Time by 105X and Reduce Accuracy Degradation by 10.8X

Authors: Khwa, W. S., Akarvardar, K., Chen, Y. S., Chiu, Y. C., Liu, J. C., Wu, J. J., Lee, H. Y., Yu, S. M., Lee, C. H., Chen, T. C., Lin, Y. C., Hsu, C. F., Lee, T. Y., Ku, T. K., Kuo, C. H., Wu, J. Y., Bao, X. Y., Chang, C. S., Chih, Y. D., Wong, H.-S. P., Chang, M. F.

Source: 2021 Symposium on VLSI Technology VLSI Technology, 2021 Symposium on. :1-2 Jun, 2021

Relation: 2021 Symposium on VLSI Technology

Low-voltage (~1.3V), Arsenic Free Threshold Type Selector with Ultra High Endurance (> 1011) for High Density 1S1R Memory Array

Authors: Wu, C. H., Lee, C. M., Chen, Y. S., Lee, H. Y., Ambrosi, E., Hsu, C. F., Vaziri, S., Chen, Y. Y., Nien, C. H., Hwang, R. L., Liao, P. J., Hou, D. H., Lee, Y.-H., Lee, T. Y., Chen, T. C., Chang, M. F., Wong, H.-S. P., Bao, X. Y.

Source: 2021 Symposium on VLSI Technology VLSI Technology, 2021 Symposium on. :1-2 Jun, 2021

Relation: 2021 Symposium on VLSI Technology

Cold MRAM as a Density Booster for Embedded NVM in Advanced Technology

Authors: Chiang, H. L., Wang, J. F., Chen, T. C., Chiang, T. W., Bair, C., Tan, C. Y., Huang, L. J., Yang, H. W., Chuang, J. H., Lee, H. Y., Chiang, K., Shen, K. H., Lee, Y. J., Wang, R., Liu, C. W., Wang, T., Bao, X., Wang, E., Cai, J., Lin, C. T., Chuang, H., Wong, H. S. P., Chang, M. F.

Source: 2021 Symposium on VLSI Technology VLSI Technology, 2021 Symposium on. :1-2 Jun, 2021

Relation: 2021 Symposium on VLSI Technology

Low variability high endurance and low voltage arsenic-free selectors based on GeCTe

Authors: Ambrosi, E., Wu, C. H., Lee, H. Y., Chang, P. C., Hsu, C. F., Lee, C. M., Chang, C. C., Chen, Y. Y, Heh, D. W., Hou, D. H., Liao, P. J., Lee, T. Y., Chang, M. F., Wong, H.-S. P., Bao, X. Y.

Source: 2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :28.5.1-28.5.4 Dec, 2021

Relation: 2021 IEEE International Electron Devices Meeting (IEDM)

3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrOx

Authors: Lin, Y. D., Lee, H. Y., Tang, Y. T., Yeh, P. C., Yang, H. Y., Yeh, P. S., Wang, C. Y., Su, J. W., Li, S. H., Sheu, S. S., Hou, T. H., Lo, W. C., Lee, M. H., Chang, M. F., King, Y. C., Lin, C. J.

Source: 2019 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2019 IEEE International. :15.3.1-15.3.4 Dec, 2019

Relation: 2019 IEEE International Electron Devices Meeting (IEDM)

Low ${\rm VDDmin}$ Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

Authors: Chang, M.-F., Wu, J.-J., Chien, T.-F., Liu, Y.-C., Yang, T.-C., Shen, W.-C., King, Y.-C., Lin, C. J., Lin, K.-F., Chih, Y.-D., Chang, J.

Source: IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 50(11):2786-2795 Nov, 2015

An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros

Authors: Chang, M.-F., Lin, Y.-F., Liu, Y.-C., Wu, J.-J., Shen, S.-J., Tsai, W.-C., Chih, Y.-D.

Source: IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 50(9):2188-2198 Sep, 2015

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

Authors: Hung, C.-H., Chang, M.-F., Yang, Y.-S., Kuo, Y.-J., Lai, T.-N., Shen, S.-J., Hsu, J.-Y., Hung, S.-N., Lue, H.-T., Shih, Y.-H., Huang, S.-L., Chen, T.-W., Chen, T. S., Chen, C. K., Hung, C.-Y., Lu, C.-Y.

Source: IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 50(6):1491-1501 Jun, 2015

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Authors: Chang, M.-F., Lee, A., Chen, P.-C., Lin, C. J., King, Y.-C., Sheu, S.-S., Ku, T.-K.

Source: IEEE Journal on Emerging and Selected Topics in Circuits and Systems IEEE J. Emerg. Sel. Topics Circuits Syst. Emerging and Selected Topics in Circuits and Systems, IEEE Journal on. 5(2):183-193 Jun, 2015

A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia

Authors: Chiu, S.-W., Wang, J.-H., Chang, K.-H., Chang, T.-H., Wang, C.-M., Chang, C.-L., Tang, C.-T., Chen, C.-F., Shih, C.-H., Kuo, H.-W., Wang, L.-C., Chen, H., Hsieh, C.-C., Chang, M.-F., Liu, Y.-W., Chen, T.-J., Yang, C.-H., Chiueh, H., Shyu, J.-M., Tang, K.-T.

Source: IEEE Transactions on Biomedical Circuits and Systems IEEE Trans. Biomed. Circuits Syst. Biomedical Circuits and Systems, IEEE Transactions on. 8(6):765-778 Dec, 2014

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

Authors: Chang, M.-F., Kuo, C.-C., Sheu, S.-S., Lin, C.-J., King, Y.-C., Chen, F. T., Ku, T.-K., Tsai, M.-J., Wu, J.-J., Chih, Y.-D.

Source: IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 49(4):908-916 Apr, 2014

Predictive energy management strategies for hybrid vehicles

Authors: Salman, M., Chang, M.-F., Chen, J.-S..

Source: 2005 IEEE Vehicle Power and Propulsion Conference Vehicle power and propulsion Vehicle Power and Propulsion, 2005 IEEE Conference. :21-25 2005

Relation: 2005 IEEE Vehicle Power and Propulsion Conference