Strained Silicon-on-Insulator Platform for Co-Integration of Logic and RF—Part II: Comb-Like Device Architecture

Authors: Liang, J., Sun, C., Xu, H., Kong, E.Y., Nguyen, B., Schwarzenbach, W., Maleville, C., Berthelon, R., Weber, O., Arnaud, F., Thean, A.V., Gong, X.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 69(4):1769-1775 Apr, 2022

Improving Ge-rich GST ePCM reliability through BEOL engineering

Authors: Redaelli, A., Gandolfo, A., Samanni, G., Gomiero, E., Petroni, E., Scotti, L., Lippiello, A., Mattavelli, P., Jasse, J., Codegoni, D., Serafini, A., Ranica, R., Boccaccio, C., Sandrini, J., Berthelon, R., Grenier, JC., Weber, O., Turgis, D., Valery, A., Del Medico, S., Caubet, V., Reynard, JP., Dutartre, D., Favennec, L., Conte, A., Disegni, F., De Tomasi, M., Ventre, A., Baldo, M., Ielmini, D., Maurelli, A., Ferreira, P., Arnaud, F., Piazza, F., Cappelletti, P., Annunziata, R., Gonella, R.

Source: ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC) Solid-State Device Research Conference (ESSDERC), ESSDERC 2021 - IEEE 51st European. :231-234 Sep, 2021

Relation: ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC)

BEOL Process Effects on ePCM Reliability

Authors: Redaelli, A., Gandolfo, A., Samanni, G., Gomiero, E., Petroni, E., Scotti, L., Lippiello, A., Mattavelli, P., Jasse, J., Codegoni, D., Serafini, A., Ranica, R., Boccaccio, C., Sandrini, J., Berthelon, R., Grenier, J., Weber, O., Turgis, D., Valery, A., Medico, S.D., Caubet, V., Reynard, J., Dutartre, D., Favennec, L., Conte, A., Disegni, F., De Tomasi, M., Ventre, A., Baldo, M., Ielmini, D., Maurelli, A., Ferreira, P., Arnaud, F., Piazza, F., Cappelletti, P., Annunziata, R., Gonella, R.

Source: IEEE Journal of the Electron Devices Society IEEE J. Electron Devices Soc. Electron Devices Society, IEEE Journal of the. 10:563-568 2022

Strained Silicon-on-Insulator Platform for Cointegration of Logic and RF—Part I: Implant-Induced Strain Relaxation

Authors: Sun, C., Xu, H., Liang, J., Kong, E.Y.-., Nguyen, B., Schwarzenbach, W., Maleville, C., Berthelon, R., Weber, O., Arnaud, F., Wang, X., Thean, A.V.-., Gong, X.

Source: IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 68(4):1425-1431 Apr, 2021

A New BJT Selector for sub-0.02µm2 High Density Embedded PCM Memory in FDSOI CMOS Technology

Authors: Weber, O., Pigot, C., Berthelon, R., Gandolfo, A., Mattavelli, P., Jasse, J., Samanni, G., Gomiero, E., Richard, E., Grenier, J. C., Ranica, R., Chouteau, S., Beneyton, R., Duclaux, B., Beylier, C., Pelissier, D., Gallon, C., Toulouse, C., Jenny, C., Croisy, M., Borowiak, C., Haendler, S., Ogier, J.L., Batail, E., Gilibert, F., Boivin, P., Turgis, D., Conte, A., Disegni, F., Redaelli, A., Annunziata, R., Cappelletti, P., Piazza, F., Ferreira, P., Arnaud, F.

Source: 2021 Symposium on VLSI Technology VLSI Technology, 2021 Symposium on. :1-2 Jun, 2021

Relation: 2021 Symposium on VLSI Technology

Investigation of SiGe channel introduction in FDSOI SRAM cell pFET and assessment of the Complementary-SRAM

Authors: Berthelon, R., Andrieu, F., Giraud, B., Rozeau, O., Weber, O., Arnaud, F., Vinet, M.

Source: 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Ultimate Integration on Silicon (EUROSOI-ULIS), 2018 Joint International EUROSOI Workshop and International Conference on. :1-4 Mar, 2018

Relation: 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

Heater system optimization for robust ePCM reliability and scalability in 28nm FDSOI technology

Authors: Ranica, R., Berthelon, R., Gandolfo, A., Samanni, G., Gomiero, E., Jasse, J., Mattavelli, P., Sandrini, J., Querre, M., Le-Friec, Y., Poulet, J., Caubet, V., Favennec, L., Boccaccio, C., Ghezzi, G., Gallon, C., Grenier, JC., Dumont, B., Weber, O., Villaret, A., Beneyton, R., Cherault, N., Ristoiu, D., Del Medico, S., Kermarrec, O., Reynard, JP., Boivin, P., Souhaite, A., Desvoivres, L., Chouteau, S., Sassoulas, PO., Clement, L., Valery, A., Petroni, E., Turgis, D., Lippiello, A., Scotti, L., Disegni, F., Ventre, A., Ornaghi, D., De Tomasi, M., Maurelli, A., Conte, A., Arnaud, F., Redaelli, A., Annunziata, R., Cappelletti, P., Piazza, F., Ferreira, P., Gonella, R., Ciantar, E.

Source: 2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :28.1.1-28.1.4 Dec, 2021

Relation: 2021 IEEE International Electron Devices Meeting (IEDM)

Mechanical simulations of BOX creep for strained FDSOI

Authors: Berthelon, R., Andrieu, F., Mathieu, B., Dutartre, D., Le Royer, C., Vinet, M., Claverie, A.

Source: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Ultimate Integration on Silicon (EUROSOI-ULIS), 2017 Joint International EUROSOI Workshop and International Conference on. :91-94 Apr, 2017

Relation: 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

Crystallization Speed in Ge-Rich PCM Cells as a Function of Process and Programming Conditions

Authors: Gomiero, E., Samanni, G., Jasse, J., Jahan, C., Weber, O., Berthelon, R., Ranica, R., Favennec, L., Caubet, V., Ristoiu, D., Reynard, J.P., Clement, L., Zuliani, P., Annunziata, R., Arnaud, F.

Source: IEEE Journal of the Electron Devices Society IEEE J. Electron Devices Soc. Electron Devices Society, IEEE Journal of the. 7:517-521 2019

Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration

Authors: Berthelon, R., Andrieu, F., Perreau, P., Baylac, E., Pofelski, A., Josse, E., Dutartre, D., Claverie, A., Haond, M.

Source: 2016 46th European Solid-State Device Research Conference (ESSDERC) Solid-State Device Research Conference (ESSDERC), 2016 46th European. :127-130 Sep, 2016

Relation: ESSDERC 2016 - 46th European Solid-State Device Research Conference

High Density Embedded PCM Cell in 28nm FDSOI Technology for Automotive Micro-Controller Applications

Authors: Arnaud, F., Ferreira, P., Piazza, F., Gandolfo, A., Zuliani, P., Mattavelli, P., Gomiero, E., Samanni, G., Jasse, J., Jahan, C., Reynard, J. P., Berthelon, R., Weber, O., Villaret, A., Dumont, B., Grenier, J. C., Ranica, R., Gallon, C., Boccaccio, C., Souhaite, A., Desvoivres, L., Ristoiu, D., Favennec, L., Caubet, V., Delmedico, S., Cherault, N., Beneyton, R., Chouteau, S., Sassoulas, P. O., Clement, L., Boivin, P., Turgis, D., Disegni, F., Ogier, J. L., Federspiel, X., Kermarrec, O., Molgg, M., Viscuso, A., Annunziata, R., Maurelli, A., Cappelletti, P., Ciantar, E.

Source: 2020 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2020 IEEE International. :24.2.1-24.2.4 Dec, 2020

Relation: 2020 IEEE International Electron Devices Meeting (IEDM)

Novel Fine-Grain Back-Bias Assist Techniques for 14nm FDSOI Top-Tier SRAMs integrated in 3D-Monolithic

Authors: Bosch, D., Andrieu, F., Ciampolini, L., Makosiej, A., Weber, O., Garros, X., Lacord, J., Cluzel, J., Esmanhotto, E., Rios, M., Lang, S., Giraud, B., Berthelon, R., Cibrario, G., Brunet, L., Batude, P., Fenouillet-Beranger, C., Lattard, D., Colinge, J. P., Balestra, F., Vinet, M.

Source: 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) VLSI Technology, Systems and Application (VLSI-TSA), 2019 International Symposium on. :1-2 Apr, 2019

Relation: 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

Impact of the design layout on threshold voltage in SiGe channel UTBB-FDSOI pMOSFET

Authors: Berthelon, R., Andrieu, F., Ortolland, S., Nicolas, R., Poiroux, T., Baylac, E., Dutartre, D., Josse, E., Claverie, A., Haond, M.

Source: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Ultimate Integration on Silicon (EUROSOI-ULIS), 2016 Joint International EUROSOI Workshop and International Conference on. :88-91 Jan, 2016

Relation: 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs

Authors: Andrieu, F., Casse, M., Baylac, E., Perreau, P., Nier, O., Rideau, D., Berthelon, R., Pourchon, F., Pofelski, A., De Salvo, B., Gallon, C., Mazzocchi, V., Barge, D., Gaumer, C., Gourhant, O., Cros, A., Barral, V., Ranica, R., Planes, N., Schwarzenbach, W., Richard, E., Josse, E., Weber, O., Arnaud, F., Vinet, M., Faynot, O., Haond, M.

Source: 2014 44th European Solid State Device Research Conference (ESSDERC) Solid State Device Research Conference (ESSDERC), 2014 44th European. :106-109 Sep, 2014

Relation: ESSDERC 2014 - 44th European Solid State Device Research Conference

Design Technology Co-Optimization in advanced FDSOI CMOS around the Minimum Energy Point: body biasing and within-cell VT-mixing

Authors: Andrieu, F., Pirro, L., Berthelon, R., Morgan, J., Cibrario, G., Wiatr, M., Hoentschel, J., Vinet, M.

Source: 2018 IEEE Symposium on VLSI Technology VLSI Technology, 2018 IEEE Symposium on. :153-154 Jun, 2018

Relation: 2018 IEEE Symposium on VLSI Technology

Towards 500°C SPER activated devices for 3D sequential integration

Authors: Micout, J., Sklenard, B., Batude, P., Berthelon, R., Rafhay, Q., Lacord, J., Mathieu, B., Pasini, L., Saghi, Z., Delaye, V., Brunet, L., Fenouillet-Beranger, C., Joblot, S., Mazen, F., Mazzocchi, V., Colinge, J-P., Ghibaudo, G., Vinet, M.

Source: 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017 IEEE. :1-2 Oct, 2017

Relation: 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

Impact of strain on access resistance in planar and nanowire CMOS devices

Authors: Berthelon, R., Andneu, F., Triozon, F., Casse, M., Bourdet, L., Ghibaudo, G., Rideau, D., Niquet, Y.M., Barraud, S., Nguyen, P., Le Royer, C., Lacord, J., Tabone, C., Rozeau, O., Dutartre, D., Claverie, A., Josse, E., Andrieu, F., Vinet, M.

Source: 2017 Symposium on VLSI Technology VLSI Technology, 2017 Symposium on. :T224-T225 Jun, 2017

Relation: 2017 Symposium on VLSI Technology

Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory

Authors: Arnaud, F., Zuliani, P., Reynard, J.P., Gandolfo, A., Disegni, F., Mattavelli, P., Gomiero, E., Samanni, G., Jahan, C., Berthelon, R., Weber, O., Richard, E., Barral, V., Villaret, A., Kohler, S., Grenier, J.C., Ranica, R., Gallon, C., Souhaite, A., Ristoiu, D., Favennec, L., Caubet, V., Delmedico, S., Cherault, N., Beneyton, R., Chouteau, S., Sassoulas, P.O., Vernhet, A., Le Friec, Y., Domengie, F., Scotti, L., Pacelli, D., Ogier, J.L., Boucard, F., Lagrasta, S., Benoit, D., Clement, L., Boivin, P., Ferreira, P., Annunziata, R., Cappelletti, P.

Source: 2018 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2018 IEEE International. :18.4.1-18.4.4 Dec, 2018

Relation: 2018 IEEE International Electron Devices Meeting (IEDM)

Smart solutions for efficient dual strain integration for future FDSOI generations

Authors: Bonnevialle, A., Le Royer, C., Morand, Y., Reboh, S., Plantier, C., Rambal, N., Pedini, J.-P., Kerdiles, S., Besson, P., Hartmann, J.-M., Marseilhan, D., Mathieu, B., Berthelon, R., Casse, M., Andrieu, F., Rouchon, D., Weber, O., Boeuf, F., Haond, M., Claverie, A., Vinet, M.

Source: 2016 IEEE Symposium on VLSI Technology VLSI Technology, 2016 IEEE Symposium on. :1-2 Jun, 2016

Relation: 2016 IEEE Symposium on VLSI Technology

Design / technology co-optimization of strain-induced layout effects in 14nm UTBB-FDSOI CMOS: Enablement and assessment of continuous-RX designs

Authors: Berthelon, R., Andrieu, F., Josse, E., Bingert, R., Weber, O., Serret, E., Aurand, A., Delmedico, S., Farys, V., Bernicot, C., Bechet, E., Bernard, E., Poiroux, T., Rideau, D., Scheer, P., Baylac, E., Perreau, P., Jaud, M.A., Lacord, J., Petitprez, E., Pofelski, A., Ortolland, S., Sardin, P., Dutartre, D., Claverie, A., Vinet, M., Marin, J.C., Haond, M.

Source: 2016 IEEE Symposium on VLSI Technology VLSI Technology, 2016 IEEE Symposium on. :1-2 Jun, 2016

Relation: 2016 IEEE Symposium on VLSI Technology