36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating

Authors: Lin, Mu-Shan, Tsai, Chien-Chun, Li, Shenggao, Chen, Wei-Chih, Huang, Wen-Hung, Chen, Yu-Chi, Huang, Yu-Jie, Drake, Alan, Wen, Chin-Hua, Ranucci, Paul, Kuo, Hsin-Hung, Yin, Aidong, Yang, Shu-Chun, Mahmoudi, Farsheed, Ke, Han-Tzung, Li, Chao-Chieh, Cheng, Nai-Chen, Wang, Jimmy, Lin, Kevin, Liao, Harry, Huang, Jie-Ren, Wu, Meng-Hsuan, Hsieh, Kenny Cheng-Hsiang, Amatruda, Nicholas, Polanco, William, King, David, Basso, Todd, Kashem, Anwar

Source: 2025 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2025 IEEE International. 68:586-588 Feb, 2025

Relation: 2025 IEEE International Solid-State Circuits Conference (ISSCC)

Digital counter segmented into short and long access time memory

DIGITAL COUNTER SEGMENTED INTO SHORT AND LONG ACCESS TIME MEMORY

Apparatus and method for synchronizing multiple threads in an out-of-order microprocessor

CGaAs PowerPC FXU.

Authors: Drake, Alan J., Basso, Todd D., Gold, Spencer M., Kraver, Keith L., Parakh, Phiroze N., Gauthier, Claude R., Stetson, P. Sean, Brown, Richard B.

Source: Proceedings of the 37th Annual Design Automation Conference; 6/1/2000, p730-735, 6p