15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes

Authors: Lin, Ku-Feng, Noguchi, Hiroki, Shih, Yi-Chun, Yuh, Perng-Fei, Lee, Yuan-Jen, Chang, Tung-Cheng, Huang, Sheng-Po, Lin, Yu-Fan, Lee, Chun-Ying, Huang, Yen-Hsiang, Tsai, Jui-Che, Adham, Saman, Noel, Peter, Yazdi, Ramin, Gershoig, Marat, Shin, YangJae, Joshi, Vineet, Wong, Ted, Jiang, Meng-Ru, Wu, J. J., Cheng, Chun-Tai, Wang, Yu-Jen, Chuang, Harry, Chih, Yu-Der, Wang, Yih, Chang, Tsung-Yung Jonathan

Source: 2024 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2024 IEEE International. 67:292-294 Feb, 2024

Relation: 2024 IEEE International Solid-State Circuits Conference (ISSCC)

34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell

Authors: Fujiwara, Hidehiro, Mori, Haruki, Zhao, Wei-Chang, Khare, Kinshuk, Lee, Cheng-En, Peng, Xiaochen, Joshi, Vineet, Chuang, Chao-Kai, Hsu, Shu-Huan, Hashizume, Takeshi, Naganuma, Toshiaki, Tien, Chen-Hung, Liu, Yao-Yi, Lai, Yen-Chien, Lee, Chia-Fu, Chou, Tan-Li, Akarvardar, Kerem, Adham, Saman, Wang, Yih, Chih, Yu-Der, Chen, Yen-Huei, Liao, Hung-Jen, Chang, Tsung-Yung Jonathan

Source: 2024 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2024 IEEE International. 67:572-574 Feb, 2024

Relation: 2024 IEEE International Solid-State Circuits Conference (ISSCC)

A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations

Authors: Fujiwara, Hidehiro, Mori, Haruki, Zhao, Wei-Chang, Chuang, Mei-Chen, Naous, Rawan, Chuang, Chao-Kai, Hashizume, Takeshi, Sun, Dar, Lee, Chia-Fu, Akarvardar, Kerem, Adham, Saman, Chou, Tan-Li, Sinangil, Mahmut Ersin, Wang, Yih, Chih, Yu-Der, Chen, Yen-Huei, Liao, Hung-Jen, Chang, Tsung-Yung Jonathan

Source: 2022 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2022 IEEE International. 65:1-3 Feb, 2022

Relation: 2022 IEEE International Solid-State Circuits Conference (ISSCC)

A Reliable, Low-Cost, Low-Energy Physically Unclonable Function Circuit Through Effective Filtering

Authors: Lu, Shih-Lien, Lee, Cheng-En, Noel, Peter, Adham, Saman, Wong, Ted, Chang, Jonathan

Source: 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) VLSI Design, Automation and Test (VLSI-DAT), 2019 International Symposium on. :1-4 Apr, 2019

Relation: 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

The importance of DFX, a foundry perspective

Authors: Adham, Saman, Chang, Jonathan, Liao, H.J., Hung, John, Hsieh, Ting-Hua

Source: 2014 International Test Conference Test Conference (ITC), 2014 IEEE International. :1-6 Oct, 2014

Relation: 2014 IEEE International Test Conference (ITC)

A novel DFT architecture for 3DIC test, diagnosis and repair

Authors: Lee, Mincent, Adham, Saman, Wang, Min-Jer, Peng, Ching-Nen, Lin, Hung-Chih, Hsu, Sen-Kuei, Chen, Hao

Source: Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on. :1-4 Apr, 2014

Relation: 2014 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoSTM/3D ICs

Authors: Goel, Sandeep Kumar, Min-Jer-Wang, Adham, Saman, Mehta, Ashok, Lee, Frank

Source: Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on. :1-4 Apr, 2014

Relation: 2014 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study

Authors: Goel, Sandeep Kumar, Adham, Saman, Wang, Min-Jer, Chen, Ji-Jan, Huang, Tze-Chiang, Mehta, Ashok, Lee, Frank, Chickermane, Vivek, Keller, Brion, Valind, Thomas, Mukherjee, Subhasish, Sood, Navdeep, Cho, Jeongho, Lee, Hayden Hyungdong, Choi, Jungi, Kim, Sangdoo

Source: 2013 IEEE International Test Conference (ITC) Test Conference (ITC), 2013 IEEE International. :1-10 Sep, 2013

Relation: 2013 IEEE International Test Conference (ITC)

Gate-oxide-short defect analysis and fault modeling in FinFETs

Authors: Dibaj, Roya, Al-Khalili, Dhamin, Shams, Maitham, Adham, Saman

Source: In Microelectronics Reliability February 2022 129

An extra low-power 1Tbit/s bandwidth PLL/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application

Authors: Lin, Mu-Shan, Tsai, Chien-Chun, Chang, Chih-Hsien, Huang, Wen-Hung, Hsu, Ying-Yu, Yang, Shu-Chun, Fu, Chin-Ming, Chou, Mao-Hsuan, Huang, Tien-Chien, Chen, Ching-Fang, Huang, Tze-Chiang, Adham, Saman, Wang, Min-Jer, Shen, William Wu, Mehta, Ashok

Source: 2013 Symposium on VLSI Technology VLSI Technology (VLSIT), 2013 Symposium on. :C16-C17 Jun, 2013

Relation: 2013 Symposium on VLSI Technology

Improved Core Isolation and Access for Hierarchical Embedded Test

Authors: Nadeau-Dostie, Benoit, Adham, Saman M.I., Abbott, Russell

Source: IEEE Design & Test of Computers IEEE Des. Test. Comput. Design & Test of Computers, IEEE. 26(1):18-25 Jan, 2009

Mechanisms for built-in self test and repair for memory devices

Mechanisms for built-in self test and repair for memory devices

Mechanisms for built-in self repair of memory devices using failed bit maps and obvious repairs

Memory repair circuit and method

Method and test circuit for testing memory internal write enable

Linking diagnostic software to hardware self-test in telecom systems.

Authors: Adham, Saman M. I., Brough, Ken, Ecroyd, Bruce

Source: IEEE Communications Magazine; June 1999, Vol. 37 Issue 6, p79-83, 5p

Scan-based BIST fault diagnosis.

Authors: Wu, Yuejian, Adham, Saman M. I.

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; February 1999, Vol. 18 Issue 2, p203-211, 9p

Self-testable digital signal processor and method for self-testing of integrating circuits including DSP data paths

Self-testable digital integrator